參數(shù)資料
型號: TSB43AA82PGE
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144
封裝: PLASTIC, QFP-144
文件頁數(shù): 83/146頁
文件大小: 770K
代理商: TSB43AA82PGE
315
3.4.16 CRF Status Register at 40h
This register defaults to 1000 004Bh and, except for the bits specified, is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
0
CRFFul
R/O
CRF full flag. While the CRF is full, CRFFul is set to 1 and writes are ignored. Otherwise, CRFFul is set to 0.
This bit defaults to 0 and is set to 0 on a bus reset.
1
CRFAFl
R/O
CRF almost-full flag. When the CRF can accept only one more quadlet write, CRFAFl is set to 1.
Otherwise, CRFAFl is set to 0. This bit defaults to 0 and is set to 0 on a bus reset.
2
CRFAEm
R/O
CRF almost-empty flag. While the CRF has only one quadlet in it, CRFAEm is set to 1. Otherwise,
CRFAEm is set to 0. This bit defaults to 0 and is set to 0 on a bus reset.
3
CRFEmp
R/O
CRF empty flag. While the CRF is empty, CRFEmp is set to 1. Otherwise, CRFEmp is set to 0. This bit
defaults to 1 and is set to 1 on a bus reset.
46
Reserved
N/A
Reserved
715
CRFThere
R/O
CRF there. The number of quadlets received in the CRF. This bit defaults to 0 and is set to 0 on a bus reset.
16
CRFCD
R/O
CRF control bit. When the first quadlet of a packet is read from the CRF data (88h) register, CRFCD is set
to 1. This bit defaults to 0 and is set to 0 on a bus reset.
1718
Reserved
N/A
Reserved
19
CRFClr
S/C
CRF clear control bit. When CRFClr is set to 1, the CRF is cleared. This bit clears itself after the CRF is
cleared. This bit defaults to 0 and is cleared on a bus reset.
2022
Reserved
N/A
Reserved
2331
CRF_Size
R/W
CRF size control bits. CRF_Size is equal to the CRF size number in quadlets.
The minimum size is CORB_SIZE at 44h. This field defaults to 4Bh and is unaffected by a bus reset.
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