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參數資料
| 型號： | TSB43AA82GGW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176 |
| 封裝： | PLASTIC, BGA-176 |
| 文件頁數： | 31/146頁 |
| 文件大?。?/td> | 770K |
| 代理商： | TSB43AA82GGW |
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114
Table 11-2. Base Register Field Descriptions (Continued)
FIELD
SIZE
TYPE
DESCRIPTION
CTOI
1
R/W
Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during tree-ID start,
and may indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset, or by writing a 1 to
this bit.
If the CTOI and WDIE bits are both set and the LLC is or becomes inactive, the PHY will activate the LINKON
output to notify the LLC to service the interrupt.
Note: If the network is configured in a loop, only those nodes that are part of the loop will generate a
configuration time-out interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID process to
complete and then generate a state time-out interrupt and bus reset.
CPSI
1
R/W
Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low indicating
that cable power may be too low for reliable operation. This bit is reset to 1 by hardware reset. It can be cleared
by writing a 1 to this bit.
If the CPSI and WDIE bits are both set and the LLC is or becomes inactive, the PHY activates the LINKON
output to notify the LLC to service the interrupt.
STOI
1
R/W
State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus reset to
occur). This bit is reset to 0 by hardware reset, or by writing a 1 to this bit. If the STOI and WDIE bits are both set
and the LLC is or becomes inactive, the PHY activate the LINKON output to notify the LLC to service the
interrupt.
PEI
1
R/W
Port event interrupt. This bit is set to 1 upon a change in the bias (unless disabled), connected, disabled, or fault
bits for any port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt
enable (WDIE) bit is set, the PEI bit is set to 1 at the start of resume operations on any port. This bit is reset to 0
by hardware reset, or by writing a 1 to this bit. If the PEI bit is set (regardless of the state of the RPEI bit) and the
LLC is or becomes inactive, the PHY activates the LINKON output to notify the LLC to service the interrupt.
EAA
1
R/W
Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration
enhancements defined in P1394a (ACK-accelerated arbitration, asynchronous fly-by concatenation, and
isochronous fly-by concatenation). This bit is reset to 0 by a hardware reset and is unaffected by a bus reset.
Note: The EAA bit should be set only if the attached LLC is P1394a compliant. If the LLC is not P1394a
compliant, use of the arbitration acceleration enhancements may interfere with isochronous traffic by
excessively delaying the transmission of cycle-start packets.
EMC
1
R/W
Enable multi-speed concatenated packets. This bit enables the PHY to transmit concatenated packets of
differing speeds in accordance with the protocols defined in P1394a. This bit is reset to 0 by a hardware reset
and is unaffected by a bus reset.
Note: The use of multispeed concatenation is completely compatible with networks containing legacy IEEE Std
1394-1995 PHYs. However, use of multispeed concatenation requires that the attached LLC be P1394a
compliant.
Page_Select
3
R/W
Page-select. This field selects the register page to use when accessing register addresses 8 through 15. This
field is reset to 0 by a hardware reset and is unaffected by a bus reset.
Port_Select
4
R/W
Port-select. This field selects the port when accessing per-port status or control (e.g., when one of the port
status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset to 0 by a
hardware reset and is unaffected by a bus reset.
The port status page provides access to configuration and status information for each of the ports. The port is selected
by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. The
configuration of the port status page registers is shown in Table 113, and the corresponding field descriptions given
in Table 114. If the selected port is unimplemented, all registers in the port status page are read as 0.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB43AA82GHH | 制造商:Texas Instruments 功能描述: |
| TSB43AA82I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
| TSB43AA82IGGW | 功能描述:1394 接口集成電路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82PGE | 功能描述:1394 接口集成電路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82PGEG4 | 功能描述:1394 接口集成電路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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