參數(shù)資料
型號(hào)： TSB43AA82GGW
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176
封裝： PLASTIC, BGA-176
文件頁數(shù)： 146/146頁
文件大?。?/td> 770K
代理商： TSB43AA82GGW
87
8.4.2.3 Write Requests With Specific Address (Direct Mode)
To receive a write request using the write request for block with specified address:
Set DRFEn (90h, bit 2) to 1.
Set DRPktz (90h, bit 4) to 0 to disable the packetizer mode.
Set DRFAdrEn (C0h, bit 2) to 1 to enable write request receiving.
When write requests for block packets are received to addresses specified with DRF destination offset hi/low and DRF
destination width, the packets are received by the DRF. The following formula shows a range of receivable packet
addresses:
DRF Destination Offset
≤ Packet Address ≤ DRF Destination Offset + DRF Destination Width
where: DRF Destination Offset specifies initiator’s BusID and NodeID.
Setting DRBIdEn (C0h, bit 0) to 1 can limit the initiator BusID, and setting DRSIdEn (C0h, bit 1) to 1 can limit the
initiator NodeID. DAckPnd (90h, bit 22) controls acknowledgements of the write request packet to the DRF. When
DAckPnd is 0, the response acknowledgement is complete. When DAckPnd is 1, the response acknowledgement
is pending. When a pending acknowledgement is sent and DRespComp (90h, bit 23) is 1, the response is complete.
8.4.2.4 Packetizer
To receive data by automatically creating an SBP-2 compliant read request for block packet:
Set DRFEn (90h, bit 2) to 1. Setting DRPktz (90h, bit 4) to 1 changes to packetizer mode.
Write expected block data information into DRF control registers 13 (C4h, C8h and CCh).
Write block data information in DRF control register 0 (C0h, bits 02), and simultaneously write 10 in
DRFCtl0DRFCtl1 to start packetizer operation.
A packetizer creates and transmits a block data read request based on the block data information.
Each time a packetizer receives an expected response packet, it makes a new request and repeats this
process. When packetizer operation stops due to completion of a transaction or some errors, DRFEnd
interrupt is created, and its result is displayed on DRFSt (C0h).
8.4.2.5 Specified as a Default
Setting 1 on RUEsel (08h, bit 25) makes DRF receive packets as a default. With this, the DRF receives read/write,
command fetch packets, and ARF to each agent, and all other unspecified packets.
8.4.3
Reading DRF Through the CFR
To read DRF data through the CFR:
Set DRDSel (90h,bit28) to 0. The microcontroller can get packets in their respective order by reading the
DRF data (ACh) register.
NOTE: DRF data can be read through the CFR or the bulky interface (see Section 8.4.4). These
can be used individually or in combination.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB43AA82GHH 制造商:Texas Instruments 功能描述:
TSB43AA82I 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 INTEGRATED PHY AND LINK LAYER CONTROLLER
TSB43AA82IGGW 功能描述:1394 接口集成電路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82PGE 功能描述:1394 接口集成電路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82PGEG4 功能描述:1394 接口集成電路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
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