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參數資料
| 型號： | TSB43AA82GGW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176 |
| 封裝： | PLASTIC, BGA-176 |
| 文件頁數： | 118/146頁 |
| 文件大?。?/td> | 770K |
| 代理商： | TSB43AA82GGW |
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47
4.3.2.5 Resume Packet
The reception of the resume packet, shown in Figure 48, causes any node to resume operations for all PHY ports
that are both connected and suspended. This is equivalent to setting the resume variable TRUE for each of these
ports. The resume packet is a broadcast packet, there is no reply. Field descriptions for the resume packet are shown
in Table 47.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
PHY_ID
0
Type (Fh)
0
1
0
Logical inverse of first quadlet
1
Figure 48. Resume Packet
Table 47. Resume Packet Descriptions
FIELD NAME
DESCRIPTION
PHY_ID
Physical node identifier of the destination of this packet
Type
Extended PHY packet type
Fh - indicates resume packet
4.4
Asynchronous Receive FIFO (ARF)
Asynchronous receive refers to the use of the ARF interface. It is configurable in register 30h (ARF status register).
The ARF receives the response of packets transmitted from the ATF. The ARF also receives request packets from
other nodes, except packets meant for the agent. The received packets are stored in ARF FIFO in the format
described below. The host accesses the packets in the ARF through register 80h.
4.4.1
Generic Quadlet and Block Receive
The quadlet-receive format is shown in Figure 49. The first quadlet is a packet token and contains packet-control
information. The first 16 bits of the second quadlet contain the destination bus and node number, and the remaining
16 bits contain packet-control information. The first 16 bits of the third quadlet contain the bus and node number of
the source, and the unreserved 4 bits of the third quadlet contain packet-control information. The fifth quadlet contains
data that was used by write requests and read responses. For read requests and write responses, the quadlet data
field is omitted.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
status
Reserved
spd
Reserved
ack
destination ID
tLabel
rt
tCode
prior
source ID
rCode
Reserved
quadlet data
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 49. Generic Receive Format of Packet With Quadlet Data
The block-receive format is shown in Figure 410 and field descriptions are shown in Table 48. The first quadlet is
a packet token and contains packet-control information. The first 16 bits of the second quadlet contain the bus and
node number of the destination node, and the last 16 bits contain packet-control information. The first 16 bits of the
third quadlet contain the bus and node number of the source node, and the last 16 bits of the third quadlet and all
of the fourth quadlet contain the 48-bit, quadlet-aligned destination offset address. All remaining quadlets contain
data that is used only for write requests and read responses. For block read requests and block write responses, the
data field is omitted.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB43AA82GHH | 制造商:Texas Instruments 功能描述: |
| TSB43AA82I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
| TSB43AA82IGGW | 功能描述:1394 接口集成電路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82PGE | 功能描述:1394 接口集成電路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82PGEG4 | 功能描述:1394 接口集成電路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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