- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384031 > TSB14C01AMHV (Texas Instruments, Inc.) Circular Connector; No. of Contacts:79; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:20-35 RoHS Compliant: No PDF資料下載
參數(shù)資料
| 型號(hào)： | TSB14C01AMHV |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:79; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:20-35 RoHS Compliant: No |
| 中文描述： | 5V的電機(jī)及電子學(xué)工程師聯(lián)合會(huì)1394-1995背板收發(fā)器/仲裁者 |
| 文件頁數(shù)： | 23/31頁 |
| 文件大小： | 424K |
| 代理商： | TSB14C01AMHV |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
format of arbitration sequence
The following format for the arbitration sequence should be used:
PRIORITY
ARBITRATION NUMBER
4 bits
6 bits
arbitration sequence
Each module on the backplane has a unique 6-bit arbitration number that is equal to the node’s physical_ID.
The arbitration number is preceded by four bits of priority. The MSB of the priority field is transmitted first.
The LSB of the priority field is followed by the MSB of the arbitration number.
Dynamic assignment of priority is accommodated.
The lowest priority level (all zeroes) is reserved for fair arbitration, and the highest priority level (all ones)
is reserved for the identification of the cycle start packet.
arbitration
Unless a node is using immediate arbitration to access the bus (in which case there is no contention for the bus),
it is possible that more than one node can attempt to access the bus at a given time. Consequently, it is
necessary for a node to arbitrate for the bus in order to gain access to the bus.
NOTE
A node uses immediate arbitration to send an acknowledge. Since there is no contention for the
bus in this case, arbitration is not necessary. A node that is transmitting an acknowledge does not
arbitrate for the bus, but merely waits for an acknowledge gap to be detected before it begins
transmission. If a node is attempting to gain access to the bus without using immediate access, it
must first arbitrate for the bus.
Arbitration occurs in response to a phy arbitration request from the link. Nodes begin arbitrating once the bus
has become idle for a predetermined amount of time (the appropriate gap indication occurs). Once this happens,
nodes begin a bit-by-bit transmission of their arbitration sequence.
A node can obtain access to the bus in a limited number of ways. Since some arbitration classes allow nodes
to begin arbitration before others, nodes arbitrating with certain arbitration classes can detect that the bus is
busy before they can begin to arbitrate. In this way, certain arbitration classes can be bypassed. For example,
fair and urgent nodes do not get a chance to arbitrate when another node is sending an acknowledge or when
it is arbitrating for an isochronous transfer.
The backplane environment supports the fair, urgent, cycle_master, isochronous, and immediate arbitration
classes.
fairness intervals
The fairness protocol is based on the concept of a fairness interval. A fairness interval consists of one or more
periods of bus activity separated by short idle periods called subaction gaps and is followed by a longer idle
period known as an arbitration reset gap. At the end of each gap, bus arbitration is used to determine the next
bus owner. This concept is shown in Figure 11.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB14C01AM | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSSOP-56 | Fairchild Semiconductor Product Package Material Disclosure |
| TSSOP-8PIN | Package Dimensions |
| TSWC01622 | SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch(SONET/SDH/PDH/ATM 時(shí)鐘合成器和保護(hù)開關(guān)) |
| TTB28F400BV-B60 | LAMP FILAMENT 14V 16MM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB14C01APM | 功能描述:1394 接口集成電路 5V 50/100Mbps Backplane PLC RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14C01APMG4 | 功能描述:1394 接口集成電路 5V 50/100Mbps Backplane PLC RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14C01APMR | 功能描述:1394 接口集成電路 50/100Mbps BACKPLANE Phy Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14C01APMRG4 | 功能描述:1394 接口集成電路 5V 1Port 50/100Mbps BP Phy Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14C01HV | 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。