參數資料
型號： TSB14C01AMHV
廠商： Texas Instruments, Inc.
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:79; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:20-35 RoHS Compliant: No
中文描述： 5V的電機及電子學工程師聯合會1394-1995背板收發(fā)器/仲裁者
文件頁數： 21/31頁
文件大?。?/td> 424K
代理商： TSB14C01AMHV
TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Total Transmit Skew
Transmit Package Skew
Spatial Skew
Logic Skew
Total Receive Skew — The total skew between data and strobe in receiving data from the bus into the phy.
This is given by the following equation.
Total Receive Skew
Receive Package Skew
Spatial Skew
Receive Setup
Receive Hold
Skew Margin — The bit cell period minus all skews. This is given by the following equation.
Skew Margin
Bit Cell Period
Total Transmit Skew
Backplane Skew
Total Receive Skew
Transmit Edge Separation — The minimum time required between any two consecutive transitions of the
bus signals to ensure proper operation of data-strobe bit level encoding. Transmit edge separation is
measured from the midpoint of the signal transition to the midpoint of the next signal transition out on the
bus. Minimum transmit edge separation is the minimum bit cell period less the maximum total transmit skew.
Receive Edge Separation — The minimum time required between any two consecutive transitions of the
bus signals to ensure proper operation of data-strobe bit level decoding. Receive edge separation is
measured from the midpoint of the signal transition to the midpoint of the next signal transition out on the
bus. This is the minimum bit cell period reduced by the amount of maximum total transmit skew and
maximum backplane skew.
gap timing
A gap is a period of time during which the bus is idle (Data_Rx and Strb_Rx are unasserted). There are three
types of gaps:
Acknowledge Gap — Appears between the end of a packet and an acknowledge, as well as between
isochronous transfers. A node should detect the occurrence of an acknowledge gap after the bus has been
in an unasserted state for 4 arbitration clock times (approximately 81.38 ns), but should not assert the bus
until a total of 8 arbitration clock times (approximately 182.76 ns) have occurred. This requirement ensures
that a node is given adequate time to detect the acknowledge gap before the bus is asserted by another
node upon detecting an acknowledge gap. This includes the minimum time required to detect a BUS_IDLE
(4 arbitration clock times), as well as the maximum delay between the arbitration state machines within any
two nodes on the bus (another 4 arbitration clock times).
Subaction Gap — Appears before asynchronous transfers within a fairness interval. A node should detect
the occurrence of a subaction gap after the bus has been in an unasserted state for at least 16 arbitration
clock times (approximately 325.52 ns), but should not assert the bus until a total of 20 arbitration clock times
(approximately 406.9 ns) have occurred. This requirement ensures that a node is given adequate time to
detect the subaction gap before the bus is asserted by another node (upon detecting a subaction gap). The
duration of the subaction gap ensures that another node asserting the bus after an acknowledge gap has
been detected by this time.
Arbitration Reset Gap — Appears before asynchronous transfers when the fairness interval starts. A node
should detect the occurrence of an arbitration reset gap after the bus has been in an unasserted state for
at least 28 arbitration clock times (approximately 569.66 ns), but should not assert the bus until a total of
32 arbitration clock times (approximately 651.04 ns) have occurred. This requirement ensures that a node
is given adequate time to detect the arbitration reset gap before the bus is asserted by another node (upon
detecting an arbitration reset gap). The duration of the arbitration reset gap ensures that another node
asserting the bus after a subaction gap or an acknowledge gap has been detected by this time.
If a node is waiting for the occurrence of a particular gap, and the bus has become idle for the specified time
(e.g., 32 arbitration clock times for an arbitration reset gap), the node detects the gap and asserts the bus within
the time constraints described under the bus synchronization and propagation delay section of this document.
These constraints ensure that an asserted signal propagates through the node decision/transceiver circuitry
and onto the bus soon enough to allow arbitration to occur properly.
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相關代理商/技術參數
參數描述
TSB14C01APM 功能描述:1394 接口集成電路 5V 50/100Mbps Backplane PLC RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB14C01APMG4 功能描述:1394 接口集成電路 5V 50/100Mbps Backplane PLC RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB14C01APMR 功能描述:1394 接口集成電路 50/100Mbps BACKPLANE Phy Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB14C01APMRG4 功能描述:1394 接口集成電路 5V 1Port 50/100Mbps BP Phy Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB14C01HV 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
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