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參數(shù)資料
| 型號(hào)： | TS83102G0BMGS |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, HERMETIC SEALED, CERAMIC, CGA-152 |
| 文件頁數(shù)： | 2/54頁 |
| 文件大?。?/td> | 2622K |
| 代理商： | TS83102G0BMGS |
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10
0935B–BDC–06/08
TS83102G0BMGS
e2v semiconductors SAS 2008
Note:
1. Output error amplitude < ±6 LSB, Fs = 2 Gsps, TJ = 110°C
2. See “Definition of Terms” on page 33.
3. 50
Ω // C
LOAD = 2 pF termination (for each single-ended output). Termination load parasitic capacitance derating value:
50 ps/pF (ECL). See “Timing Information” on page 35.
4. TOD and TDR propagation times are defined at package input/outputs. They are given for reference only. See “Propagation
5. Values for TD1 and TD2 are given for a 2 Gsps external clock frequency (50% duty cycle). For different sampling rates, apply
the following formula: TD1 = T/2 + (|TOD - TDR|) and TD2 = T/2 + (|TOD - TDR|), where T = clock period. This places the ris-
ing edge (True/False) of the differential data ready signal in the middle of the output data valid window. This gives maximum
setup and hold times for external data acquisition.
Table 3-6.
Transient and Switching Performances
Parameter
Test
Level
Symbol
Min
Typ
Max
Unit
Transient Performance
Bit error rate (1)
4
BER
10-12
Error/
sample
ADC setting time (VIN - VINB = 400 mVpp)
4
TS
1
ns
Overvoltage recovery time
4
ORT
500
ps
ADC step response rise/fall time (10% to 90%)
80
100
ps
Overshoot
4%
Ringback
2%
Switching Performance and Characteristics
Maximum clock frequency (2)
FSMax
2
2.2
Gsps
Minimum clock frequency (2)
4FSMin
150
200
Msps
Minimum clock pulse width (high)
4
TC1
0.2
0.25
2.5
ns
Minimum clock pulse width (low)
4
TC2
0.2
0.25
2.5
ns
Aperture delay (2)
4
TA
160
ps
Aperture uncertainty (2)
4
Jitter
150
200
fs rms
Output rise/fall time for DATA (20% to 80%) (3)
4
TR/TF
150
200
ps
Output rise/fall time for DATA READY (20% to 80%) (3)
4
TR/TF
150
200
ps
Data output delay (4)
4TOD
360
ps
Data ready output delay (4)
4TDR
410
ps
4
ITOD
minus
TDRI
0
50
100
ps
Output data to data ready propagation delay (5)
4
TD1
250
300
350
ps
Data ready to output data propagation delay (5)
4
TD2
150
200
250
ps
Output data pipeline delay
4
TPD
4.0
Clock
cycles
Data ready reset delay
4
TRDR
1000
ps
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