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參數(shù)資料
| 型號： | TS83102G0BMGS |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, HERMETIC SEALED, CERAMIC, CGA-152 |
| 文件頁數(shù)： | 16/54頁 |
| 文件大?。?/td> | 2622K |
| 代理商： | TS83102G0BMGS |
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23
0935B–BDC–06/08
e2v semiconductors SAS 2008
TS83102G0BMGS
Figure 6-11. SFDR vs. Input
Frequency at Fs = 1.4 Gsps
and Fs = 1.7 Gsps
Figure 6-12. SNR vs. Input
Frequency at Fs = 1.4 Gsps
and Fs = 1.7 Gsps
6.1.6
Typical Reconstructed Signals and Signal Spectrum
The ADC input signal is sampled at a full sampling rate, but the output data is 8 or 16 times decimated so
as to relax the acquisition system data rate. As a consequence, the calculation software sees an effec-
tive frequency divided by 8 or 16, compared to the ADC clock frequency used (Fs).
This does not have any impact on the FFT spectral characteristics because of the ergodicity of the sam-
ples (time average = statistic average). The input frequency is chosen to respect the coherence of the
acquisition. The spectrum is displayed from DC to Fs/2.
Figure 6-13. Fs = 1.4 Gsps and Fin = 702 MHz, –1 dBFS; Decimation Factor = 8, 32 kpoints FFT
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-30
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Fin (MHz)
SFDR
(dBc)
Fs = 1.4 Gsps
Fs = 1.7 Gsps
30
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50
55
60
0
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Fin (MHz)
SNR
(dB)
Fs = 1.4 Gsps
Fs = 1.7 Gsps
0
100
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700
800
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1000
0
5000
10000
15000
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amples
LSB
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0
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0
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=Fs/2
dBc
MHz
SFDR = -64 dBc
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參數(shù)描述 |
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| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
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