參數(shù)資料
型號(hào): TS83102G0BMGS
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152
封裝: 21 X 21 MM, 1.27 MM PITCH, HERMETIC SEALED, CERAMIC, CGA-152
文件頁數(shù): 11/54頁
文件大小: 2622K
代理商: TS83102G0BMGS
19
0935B–BDC–06/08
e2v semiconductors SAS 2008
TS83102G0BMGS
6.
Typical Characterization Results
6.1
Nominal Conditions
V
CC = 5V; 50% clock duty cycle; binary output data format; TJ = 80°C; -1 dBFS, unless otherwise
specified.
6.1.1
Typical Full Power Input Bandwidth
Vin = 1 dBFS
Gain flatness at ±0.15 dB from DC to 1.5 GHz
Full power input bandwidth at 3 dB > 3.3 GHz
Figure 6-1.
Full Power Input Bandwidth at 3 dB
6.1.2
Typical VSWR vs. Input Frequency
Figure 6-2.
VSWR Curve for VIN and CLK
-6.0
-5.5
-5.0
-4.5
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
10
0
30
0
50
0
70
0
90
0
11
00
13
00
15
00
170
0
190
0
21
00
23
00
25
00
270
0
290
0
310
0
33
00
35
00
Fin (MHz)
dBF
S
Gain Flatness (±0.15 dB)
-3 dB Bandwidth
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
0
500
1000
1500
2000
2500
3000
3500
Frequency (MHz)
VSW
R
CLK
VIN
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