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參數(shù)資料
| 型號(hào)： | TS83102G0BMGS |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, HERMETIC SEALED, CERAMIC, CGA-152 |
| 文件頁數(shù)： | 12/54頁 |
| 文件大?。?/td> | 2622K |
| 代理商： | TS83102G0BMGS |
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2
0935B–BDC–06/08
TS83102G0BMGS
e2v semiconductors SAS 2008
1.
Description
The TS83102G0BMGS is a monolithic 10-bit analog-to-digital converter, designed for digitizing wide
bandwidth analog signals at very high sampling rates of up to 2 Gsps. It uses an innovative architecture,
including an on-chip Sample and Hold (S/H). The 3.3 GHz full power input bandwidth and band flatness
performances enable the digitizing of high IF and large bandwidth signals.
Figure 1-1.
Simplified Block Diagram
2.
Functional Description
The TS83102G0BMGS is a 10-bit 2 Gsps ADC. The device includes a front-end master/slave Track and
Hold stage (Sample and Hold), followed by an analog encoding stage (Analog Quantizer), which outputs
analog residues resulting from analog quantization. Successive banks of latches regenerate the analog
residues into logical levels before entering an error correction circuit and resynchronization stage, fol-
lowed by 50
Ω differential output buffers.
The TS83102G0BMGS works in a fully differential mode from analog inputs to digital outputs. A differen-
tial Data Ready output (DR/DRB) is available to indicate when the outputs are valid and an
Asynchronous Data Ready Reset ensures that the first digitized data corresponds to the first acquisition.
The control pin B/GB (A11 of the CI-CGA package) is provided to select either a binary or gray data out-
put format. The gain control pin GA (R9 of the CI-CGA package) is provided to adjust the ADC gain
transfer function.
A Sampling Delay Adjust function (SDA) may be used to ease the interleaving of ADCs. A pattern gener-
ator is integrated on the chip for debug or acquisition setup. This function is activated through the PGEB
pin (A9 of the CI-CGA package).
An out-of-range bit (OR/ORB) indicates when the input overrides 0.5 Vpp.
A selectable decimation by 32 functions is also available for enhanced testability coverage (A10 of the
CI-CGA package), along with the die junction temperature monitoring function.
The TS83102G0BMGS uses only vertical isolated NPN transistors together with oxide isolated polysili-
con resistors, which allows enhanced radiation tolerance (over 100 kRad (Si) total dose expected
tolerance).
Sample &Hold
Clock generation
Logic block
Analog
Q
uant
izer
VIN
VINB
CLK
CLKB
PGEB
B/GB
DRRB
OR
ORB
D9
D9B
D0
D0B
GA
DR
DRB
50
SDA
DECB/
DIODE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS83102G0BVGL | 制造商:e2v technologies 功能描述:ADC SGL 2GSPS 10-BIT PARALLEL 152CBGA - Trays |
| TS83102G0CGL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
| TS83102G0GSZR5 | 制造商:e2v technologies 功能描述:TS83102G0GSZR5 - Trays |
| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
| TS831-3ID | 功能描述:監(jiān)控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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