參數(shù)資料
型號(hào)： TMS320LC545
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(20/25ns指令周期， 高性能，大并行度，特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的DSP)
中文描述： 數(shù)字信號(hào)處理器（20/25ns指令周期，高性能，大并行度，特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的數(shù)字信號(hào)處理器）
文件頁(yè)數(shù)： 33/107頁(yè)
文件大小： 2149K
代理商： TMS320LC545
TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
30
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
hardware-programmable PLL
The ’C54x and ‘LC54x can use either the internal oscillator or an external frequency source for an input clock.
The clock generation mode is determined by the CLKMD1, CLKMD2 and CLKMD3 clock mode pins except on
the ’545A, the ’546A, and the ’LC548 (see software-programmable PLL description below). Table 4 outlines the
selection of the clock mode by these pins.
Table 4. Clock Mode Configurations
MODE-SELECT PINS
CLOCK MODE
CLKMD1
CLKMD2
CLKMD3
OPTION 1
OPTION 2
0
0
0
PLL
×
3 with external source
PLL
×
2 with extenal source
PLL
×
3, internal oscillator enabled
PLL
×
1.5 with external source
Divide-by-two with external source
Stop mode
PLL
×
1 with external source
Divide-by-two, internal oscillator enabled
PLL
×
5 with external source
PLL
×
4 with external source
PLL
×
5, internal oscillator enabled
PLL
×
4.5 with external source
Divide-by-two with external source
Stop mode
PLL
×
1 with external source
Divide-by-two, internal oscillator enabled
1
1
0
1
0
0
0
1
0
0
0
1
0
1
1
1
0
1
1
1
1
Option: Option 1 or option 2 is selected when ordering the device.
Stop mode: The function of the stop mode is equivalent to that of the power-down mode of IDLE3; however, the IDLE3 instruction is recommended
rather than stop mode to realize full power saving, since IDLE3 stops clocks synchronously and can be exited with an interrupt.
software-programmable PLL (’545A, ’546A, and ’548)
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved.
Devices that have a built-in software-programmable PLL can be configured in one of two clock modes:
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved
using the PLL circuitry.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be
completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. The
CLKMD register fields are shown in Figure 6 and described below. Note that upon reset, the CLKMD register
is initialized with a predetermined value dependent only upon the state of the CLKMD1 – CLKMD3 pins (see
Table 7).
Bit #
15–12
11
10–3
2
1
0
PLLMUL
R/W
PLLDIV
R/W
PLLCOUNT
R/W
PLLON/OFF
R/W
PLLNDIV
PLLSTATUS
R/W
R
R = read, W = write
When in DIV mode (PLLSTATUS is low), PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF are don’t cares, and their contents are
indeterminate.
Figure 6. Clock Mode Control Register (CLKMD)
A
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