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參數(shù)資料
| 型號： | TMS320LC545 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(20/25ns指令周期， 高性能，大并行度，特殊指令集可有效實現(xiàn)多種復雜算法及應(yīng)用的DSP) |
| 中文描述： | 數(shù)字信號處理器（20/25ns指令周期，高性能，大并行度，特殊指令集可有效實現(xiàn)多種復雜算法及應(yīng)用的數(shù)字信號處理器） |
| 文件頁數(shù)： | 21/107頁 |
| 文件大?。?/td> | 2149K |
| 代理商： | TMS320LC545 |
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TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
central processing unit (CPU)
The CPU of the ’C54x/’LC54x devices contains:
A 40-bit arithmetic logic unit (ALU)
Two 40-bit accumulators
A
barrel shifter
A 17
×
17-bit multiplier/adder
A compare, select and store unit (CSSU)
arithmetic logic unit (ALU)
The ’C54x/’LC54x perform 2s-complement arithmetic using: a 40-bit arithmetic logic unit (ALU)
and two 40-bit
accumulators
(ACCA and ACCB). The ALU also can perform Boolean operations.
The ALU can function as two 16-bit ALUs and perform two 16-bit operations simultaneously when the C16 bit
in status register 1 (ST1) is set.
accumulators
The accumulators, ACCA and ACCB, store the output from the ALU or the multiplier / adder block; the
accumulators can also provide a second input to the ALU or the multiplier / adder. The accumulators are divided
into three parts:
Guard bits (bits 32–39)
A high-order word (bits 16–31)
A low-order word (bits 0–15)
Instructions are provided for storing the guard bits, the high- and the low-order accumulator words in data
memory, and for manipulating 32-bit accumulator words in or out of data memory. Also, any of the accumulators
can be used as temporary storage for the other.
barrel shifter
The ’C54x/’LC54x’s barrel shifter has a 40-bit input connected to the accumulator, or data memory
(CB, DB) and a 40-bit output connected to the ALU, or data memory (EB). The barrel shifter produces a left shift
of 0 to 31 bits and a right shift of 0 to 16 bits on the input data. The shift requirements are defined in the shift-count
field
(ASM) of ST1 or defined in the temporary register (TREG), which is designated as a shift-count register.
This shifter and the exponent detector normalize the values in an accumulator in a single cycle. The least
significant bits (LSBs) of the output are filled with 0s and the most significant bits (MSBs) can be either zero-filled
or sign-extended, depending on the state of the sign-extended mode bit (SXM) of ST1. Additional shift
capabilities enable the processor to perform numerical scaling, bit extraction, extended arithmetic, and overflow
prevention operations.
multiplier/adder
The multiplier / adder performs 17
×
17-bit 2s-complement multiplication with a 40-bit accumulation in a single
instruction cycle. The multiplier / adder block consists of several elements: a multiplier, adder, signed / unsigned
input control, fractional control, a zero detector, a rounder (2s-complement), overflow / saturation logic, and
TREG. The multiplier has two inputs: one input is selected from the TREG, a data-memory operand, or an
accumulator; the other is selected from the program memory, the data memory, an accumulator, or an
immediate value. The fast on-chip multiplier allows the ’C54x/’LC54x to perform operations such as
convolution, correlation, and filtering efficiently.
In addition, the multiplier and ALU together execute multiply/accumulate (MAC) computations and ALU
operations in parallel in a single instruction cycle. This function is used in determining the Euclid distance, and
in implementing symmetrical and least mean square (LMS) filters, which are required for complex DSP
algorithms.
A
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