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參數(shù)資料
| 型號： | TMS320LC545 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(20/25ns指令周期， 高性能，大并行度，特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的DSP) |
| 中文描述： | 數(shù)字信號處理器（20/25ns指令周期，高性能，大并行度，特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的數(shù)字信號處理器） |
| 文件頁數(shù)： | 30/107頁 |
| 文件大小： | 2149K |
| 代理商： | TMS320LC545 |
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TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
27
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
programmable bank-switching
Programmable bank-switching can be used to insert one cycle automatically when crossing memory-bank
boundaries inside program memory or data memory space. One cycle can also be inserted when crossing from
program-memory space to data-memory space (’C54x/’LC54x) or one program memory page to another
program memory page (’LC548 only). This extra cycle allows memory devices to release the bus before other
devices start driving the bus; thereby avoiding bus contention. The size of memory bank for the bank-switching
is defined by the bank-switching control register (BSCR).
parallel I/O ports
Each ’C54x/’LC54x device has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction
or the PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The
’C54x/’LC54x devices can interface easily with external devices through the I/O ports while requiring minimal
off-chip address-decoding circuits.
host-port interface (’C542, ’LC542, ’LC545, and ’LC548 only)
The host-port interface (HPI) is an 8-bit parallel port used to interface a host processor to the DSP device.
Information is exchanged between the DSP device and the host processor through on-chip memory that is
accessible by both the host and the DSP device. The DSP devices have access to the HPI control (HPIC)
register and the host can address the HPI memory through the HPI address register (HPIA). HPI memory is a
2K-word DARAM block that resides at 1000h to 17FFh in data memory and can also be used as
general-purpose on-chip data or program DARAM.
Data transfers of 16-bit words occur as two consecutive bytes with a dedicated pin (HBIL) indicating whether
the high or low byte is being transmitted. Two control pins, HCNTL1 and HCNTL0, control host access to the
HPIA, HPI data (with an optional automatic address increment), or the HPIC. The host can interrupt the DSP
device by writing to HPIC. The DSP device can interrupt the host with a dedicated HINT pin that the host can
acknowledge and clear.
The HPI has two modes of operation, shared-access mode (SAM) and host-only mode (HOM). In SAM, the
normal mode of operation, both the DSP device and the host can access HPI memory. In this mode,
asynchronous host accesses are resynchronized internally and, in case of conflict, the host has access priority
and the DSP device waits one cycle. The HOM capability allows the host to access HPI memory while the DSP
device is in IDLE2 (all internal clocks stopped) or in reset mode. The host can therefore access the HPI RAM
while the DSP device is in its optimal configuration in terms of power consumption.
The HPI control register has two data strobes, HDS1 and HDS2, a read/write strobe HR/W, and an address
strobe HAS, to enable a glueless interface to a variety of industry-standard host devices. The HPI is interfaced
easily to hosts with multiplexed address/data bus, separate address and data buses, one data strobe and a
read/write strobe, or two separate strobes for read and write.
The HPI supports high-speed back-to-back accesses. In the SAM, it can handle one byte every five DSP device
periods—that is, 64 MBps with a 40-MIPS DSP. The HPI is designed so that the host can take advantage of this
high bandwidth and run at frequencies up to (f
n)
÷
5, where n is the number of host cycles for an external
access and f is the DSP device frequency. In HOM, the HPI supports even higher speed back-to-back host
accesses: 1 byte every 50 ns—that is, 160 MBps, independently of the DSP device-clock rate.
A
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| TMS320LC545APBK-50 | 功能描述:IC FIXED POINT DSP 128-LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TMS320C54x 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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