參數(shù)資料
型號： TMS320DM647ZUT720
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數(shù)字媒體處理器
文件頁數(shù)： 66/166頁
文件大?。?/td> 1341K
代理商： TMS320DM647ZUT720
www.ti.com
P
6.4.2
PLL1 Controller Operating Modes
6.4.3
PLL1 Stabilization, Lock, and Reset Times
6.4.4
PLL1 Controller Input and Output Clock Electrical Data/Timing
CLKIN
2
3
4
4
5
1
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
The PLL1 controller has two modes of operation: bypass mode and PLL mode. The mode of operation is
determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, SYSREFCLK is
generated from the device input clock CLKIN1 using the divider PREDIV and the PLL multiplier PLLM. In
bypass mode, CLKIN1 is fed directly to SYSREFCLK.
All hosts (HPI, PCI, etc.) must hold off accesses to the DSP while the frequency of its internal clocks is
changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration
has completed.
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to
become stable after device power-up. The PLL should not be operated until this stabilization time has
expired.
The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in
order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the
PLL1 reset time value, see
Table 6-7
.
Table 6-7. PLL1 Stabilization, Lock, and Reset Times
MIN
150
TYP
MAX
UNIT
μ
s
μ
s
μ
s
PLL stabilization time
PLL lock time
PLL reset time
2000*C
(1)
128*C
(1)
(1)
C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.
Table 6-8. Timing Requirements for CLKIN1
(1)(2)(3)
(see
Figure 6-6
)
-720
-900
PLL MODES
x1 (Bypass), x15, x20,
x25, x30, x32
MIN
15
0.4C
0.4C
NO.
UNIT
MAX
30.3
1
2
3
4
5
t
c(CLKIN1)
t
w(CLKIN1H)
t
w(CLKIN1L)
t
t(CLKIN1)
t
J(CLKIN1)
Cycle time, CLKIN1
Pulse duration, CLKIN1 high
Pulse duration, CLKIN1 low
Transition time, CLKIN1
Period jitter, (peak-to-peak), CLKIN1
ns
ns
ns
ns
ps
1.2
100
(1)
(2)
(3)
The reference points for the rise and fall transitions are measured at 3.3-V V
MAX and V
MIN.
C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.
The PLL1 multiplier factors (x1 [BYPASS], x 15, x20, x25, x30, x32) further limit the MIN and MAX values for tc(CLKIN1). For more
detailed information on these limitations, see
Section 6.3.5
, DM647/DM648 Power and Clock Domains.
Figure 6-6. CLKIN1 Timing
Peripheral Information and Electrical Specifications
66
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