參數(shù)資料
型號(hào)： TMS320DM647ZUT720
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數(shù)字媒體處理器
文件頁數(shù)： 145/166頁
文件大?。?/td> 1341K
代理商： TMS320DM647ZUT720
www.ti.com
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6.18.1 Ethernet Subsystem Functions
SGMII 0
GMII port 0
Gigabit
MAC 0
SGMII 1
(A)
GMII port 1
2
2
2
Addr Lookup
Engine
SGMII
Port 0
Host DMA
Controller
3-port
Gigabit
Switch
Gigabit
MAC 1
Buffer
Descriptor
Memory
Configuration
Registers
REFCLK
2
2
SGMII
Port 1
MII
Serial
Mgmt
Peripheral
Bus
MDIO
Configuration
Bus
Configuration
Bus
DSP
Interrupt
Controller
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Adaptive active equalization for superior data dependent jitter tolerance in the presence of a
lossy channel
Loss of signal detector with programmable threshold levels in receive channels
Integrated receiver and transmitter termination
IEEE 802.3 gigabit Ethernet conformant
A.
SGMII port 1 is not available on DM647.
Figure 6-42. Ethernet Subsystem Block Diagram
The Ethernet Subsystem conforms to the IEEE 802.3-2002 standard. Deviating from this standard, the
GMAC module does not use the transmit coding error signal MTXER. Instead of driving the error pin when
an underflow condition occurs on a transmitted frame, the GMAC generates an incorrect checksum by
inverting the frame CRC, so that the transmitted frame will be detected as an error by the network.
In networking systems, packet transmission and reception are critical tasks. The communications port
programming interface (CPPI) protocol maximizes the efficiency of interaction between the host software
and communications modules. The CPPI block in the DM648/DM647 contains 2048 words of 32-bit buffer
descriptor memory that holds up to 512 buffer descriptors.
After reset, initialization, configuration, and auto-negotiation, the host C64x+ DSP may initiate Ethernet
transmit and receive operations.
Transmit operations are initiated by C64x+ DSP writes to the appropriate transmit channel head
descriptor pointer contained in the CPDMA block. The CPDMA TX controller then fetches the first
packet in the packet chain from memory in accordance with the CPPI protocol for the GMAC to
process before sending to the SGMII.
Receive operations are initiated by C64x+ DSP writes to the appropriate receive channel head
descriptor pointer. The CPDMA RX controller then writes packets to memory in accordance with the
CPPI protocol.
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Peripheral Information and Electrical Specifications
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TMS320DM647ZUTD1 制造商:Texas Instruments 功能描述:- Trays
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