參數(shù)資料
型號: TLV320AIC3106IGQER
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
中文描述: 低功耗立體聲音頻編解碼器的便攜式音頻/電話
文件頁數(shù): 25/102頁
文件大?。?/td> 1259K
代理商: TLV320AIC3106IGQER
www.ti.com
DSP MODE
In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and
immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.
BCLK
WCLK
0
0
T0152-01
1/fs
LSB
LSB
LSB MSB
MSB
Left Channel
Right Channel
1
1
2
2
SDIN/SDOUT
n–1
n–1
n–1
n–2
n–3
n–3
n–4
n–2
TDM DATA TRANSFER
Time-division multiplexed data transfer can be realized in any of the above transfer modes if the 256-clock bit
clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By
changing the programmable offset, the bit clock in each frame where the data begins can be changed, and the
serial data output driver (DOUT) can also be programmed to 3-state during all bit clocks except when valid data
is being put onto the bus. This allows other codecs to be programmed with different offsets and to drive their
data onto the same DOUT line, just in a different slot. For incoming data, the codec simply ignores data on the
bus except where it is expected based on the programmed offset.
TLV320AIC3106
SLAS509B–DECEMBER 2006–REVISED JUNE 2007
Figure 23. DSP Serial Bus Mode Operation
Note that the location of the data when an offset is programmed is different, depending on what transfer mode is
selected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other
in the frame. This differs from left-justified mode, where the left and right channel data will always be a
half-frame apart in each frame. In this case, as the offset is programmed from zero to some higher value, both
the left and right channel data move across the frame, but still stay a full half-frame apart from each other. This
is depicted in
Figure 24
for the two cases.
25
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