參數(shù)資料
型號: TLC320AD50IPT
廠商: Texas Instruments, Inc.
英文描述: SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION
中文描述: sigma - delta模擬接口,具有大師電路,從功能
文件頁數(shù): 72/84頁
文件大小: 447K
代理商: TLC320AD50IPT
A–2
CONTROL FUNCTION OF CONTROL BITS (Continued)
BITS
TERMINALS
FC1
D01
D00
FC0
0
1
1
1
On the next falling edge of FS, the AIC receives DAC data D15–D02 to DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of D01 and D00 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A
register. When the A
register value is negative, FS occurs earlier.
When FC0 and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 1/2 the
sampling time as measured from the falling edge of the primary FS.
1
0
1
1
On the next falling edge of FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of D01 and D00. On the next rising
edge of FS, the next ADC/DAC sample time occurs earlier by the number of MCLK
periods determined by the value contained in the A
register. When the A
register
value is negative, FS occurs later.
When FC0 and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 1/2 the
sampling time as measured from the falling edge of the primary FS.
1
1
1
1
On the next falling edge of the primary FS, the AIC receives DAC data D15–D02 at
DIN and transmits the ADC data D15–D00 from DOUT.
When FC1 and FC0 are both high or D01 and D00 are both high, the AIC initiates a
secondary FS to receive a secondary control word at DIN. The secondary FS occurs
at 1/2 the sampling time measured from the falling edge of the primary FS.
1
1
0
1
On the next falling edge of FS, the AIC receives DAC data D15–D02 to DIN and
transmits the ADC data D15–D00 from DOUT.
When D00 and D01 are high, the AIC initiates a secondary FS to receive a secondary
control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as
measured from the falling edge of the primary FS.
The phase adjustment is determined by the state of FC1 and FC0 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A
register. When the A
register value is negative, FS occurs earlier.
1
1
1
0
On the next falling edge of FS, the AIC receives DAC data D15–D02 to DIN and
transmits the ADC data D15–D00 from DOUT.
When D00 and D01 are high, the AIC initiates a secondary FS to receive a secondary
control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as
measured from the falling edge of the primary FS.
The phase adjustment is determined by the state of FC1 and FC0 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A
register. When the A
register value is negative, FS occurs earlier.
1
1
1
1
On the next falling edge of FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
When FC1 and FC0 are both high or D01 and D00 are both high, the AIC initiates a
secondary FS to receive a secondary control word at DIN. The secondary FS occurs
at 1/2 the sampling time measured from the falling edge of the primary FS.
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PDF描述
TLC320AD50(中文) Sigma-Delta Analog Interface Circuit With Master-Slave Function(Sigma-Delta 模擬接口具主從功能)
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