參數(shù)資料
型號: TLC320AD50IPT
廠商: Texas Instruments, Inc.
英文描述: SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION
中文描述: sigma - delta模擬接口,具有大師電路,從功能
文件頁數(shù): 49/84頁
文件大小: 447K
代理商: TLC320AD50IPT
4–1
4
Parameter Measurement Information
_
+
IN+ or AUX IN+
IN– or AUX IN–
To Multiplexer
Rfb
Rfb
_
+
Rfb = R for DS03 = 0 and DS02 = 1
Rfb = 2R for DS03 = 1 and DS02 = 0
Rfb = 4R for DS03 = 1 and DS02 = 1
R = 100 k
nominal
R
R
Figure 4–1. IN+ and IN– Gain-Control Circuitry
Table 4–1. Gain Control (Analog Input Signal Required for
Full-Scale Bipolar A/D-Conversion 2s Complement)
INPUT CONFIGURATION
CONTROL REGISTER 4
ANALOG INPUT
A/D CONVERSION
RESULT
DS03
0
DS02
0
All
Squelch
±
Full scale
±
Full scale
±
Full scale
Squelch
±
Half scale
±
Full scale
±
Full scale
Differential configuration
Analog input = IN+
IN
0
1
VID =
±
3 V
VID =
±
1.5 V
VID =
±
0.75 V
All
VI =
±
1.5 V
VI =
±
1.5 V
VI =
±
0.75 V
= AUX IN+ – AUX IN–
AUX IN+ AUX IN
1
0
1
1
0
0
Single-ended configuration§
Analog input = IN+ – VMID
= AUX IN+ – VMID
= AUX IN+ VMID
0
1
1
1
0
1
VDD = 5 V
VID = differential input voltage, VI = input voltage referenced to ADC VMID with IN– or AUX IN– connected to
ADC VMID. In order to minimize distortion, it is recommended that the analog input not exceed 0.1 dB below full scale.
§For single-ended inputs, the analog input voltage should not exceed the supply rails. All single-ended inputs should be
referenced to the internal reference voltage, ADC VMID, for best common-mode performance.
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