參數(shù)資料
型號(hào)： TLC320AD50IPT
廠商： Texas Instruments, Inc.
英文描述： SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION
中文描述： sigma - delta模擬接口，具有大師電路，從功能
文件頁(yè)數(shù)： 16/84頁(yè)
文件大?。?/td> 447K
代理商： TLC320AD50IPT
2–1
2
2.1
ADC Channel
Detailed Description
Definitions and Terminology
All signal processing circuits between the analog input and the digital conversion
results at DOUT
Codec Mode
The operating mode under which the device receives shift clock and frame-sync
signals from a host processor. The device has no slaves.
d
The d represents valid programmed or default data in the control register format
(see Section 2.19) when discussing other data-bit portions of the register.
Dxx
Bit position in the primary data word (xx is the bit number)
DAC Channel
All signal processing circuits between the digital data word applied to DIN and the
differential output analog signal available at OUT+ and OUT–
Data Transfer Interval The time during which data is transferred from DOUT and to DIN. This interval is 16
shift clocks regardless of whether the shift clock is internally or externally generated.
The data transfer is initiated by the falling edge of the frame-sync signal.
DSxx
Bit position in the secondary data word (xx is the bit number)
FCLK
An internal clock frequency that is a division of MCLK that controls the low-pass filter
and (sinx)/x filter clock (see Figure 1–1 and Table 1-1).
f
i
The analog input frequency of interest
Frame Sync
The falling edge of the signal that initiates the data-transfer interval. The primary
frame sync starts the primary communications, and the secondary frame sync starts
the secondary communications.
Frame Sync and
The time between falling edges of successive primary frame-sync signals
Sampling Period
Frame-Sync Interval
The time period occupied by 16 shift clocks. Regardless of the mode of operation,
there is always an internal frame-sync interval signal that goes low on the rising
edge of SCLK and remains low for 16 shift clocks. It is used for synchronization of
the serial-port internal signals. It goes high on the seventeenth rising edge of SCLK.
f
s
The sampling frequency that is the reciprocal of the sampling period.
Host
Any processing system that interfaces to DIN, DOUT, SCLK, or FS.
Master Mode
The operating mode under which the device generates and uses its own shift clock
and frame-sync signal and generates all delayed frame-sync signals necessary to
support slave devices.
Phase Adjustment
The programmed time variation from the falling edge of one frame-sync signal to the
falling edge of the next frame sync signal. The time variation is determined by the
contents of the A
′
register. Since the time between falling edges of successive
frame-sync signals is the the sampling period, the sampling period is adjusted.
Primary (Serial)
The digital data-transfer interval. Since the device is synchronous, the signal data
Communications
words from the ADC channel and to the DAC channel occur simultaneously.
Secondary (Serial)
The digital control and configuration data-transfer interval into DIN and the register
Communications
read-data cycle from DOUT. The data-transfer interval occurs when requested by
hardware or software.
Signal Data
The input signal and all of the converted representations through the ADC channel
and return through the DAC channel to the analog output. This is contrasted with
the purely digital software-control data.
Slave Mode
The operating mode under which the device receives shift clock and frame-sync
signals from a master device.
相關(guān)PDF資料
PDF描述
TLC320AD50(中文) Sigma-Delta Analog Interface Circuit With Master-Slave Function(Sigma-Delta 模擬接口具主從功能)
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