參數(shù)資料
型號： TLC320AD50IPT
廠商： Texas Instruments, Inc.
英文描述： SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION
中文描述： sigma - delta模擬接口，具有大師電路，從功能
文件頁數(shù)： 43/84頁
文件大?。?/td> 447K
代理商： TLC320AD50IPT
3–4
3.5.5
DAC Channel Signal-to-Distortion Ratio, V
DD
= 5 V, f
s
= 8 kHz
(
Unless
Otherwise Noted)
PARAMETER
TEST CONDITIONS
AV = 0 dB
MIN
64
AV = –6 dB
MIN
—
AV = –12 dB
MIN
—
UNIT
MAX
MAX
MAX
VO = –6 dB to 0 dB
VO = –12 dB to –6 dB
VO = –18 dB to –12 dB
VO = –24 dB to –18 dB
VO = –30 dB to –24 dB
VO = –36 dB to –30 dB
VO = –42 dB to –36 dB
VO = –48 dB to –42 dB
59
64
—
56
59
64
DAC channel signal-to-
distortion ratio
(see Note 8)
50
56
59
dB
44
50
56
38
44
50
32
26
38
32
44
38
NOTE 8: The input signal, VI, is the digital equivalent of a 1020-Hz sine wave (full-scale analog output at full-scale digital
input = 0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The
load impedance for the DAC output buffer is 600
from OUT+ to OUT–.
3.5.6
System Distortion, V
DD
= 5 V, f
s
= 8 kHz, FCLK = 144 kHz (Unless Otherwise
Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Single ended input (see Note 9)
Single-ended input (see Note 9)
82
Second harmonic
ADC channel
attenuation
Differential input (see Note 9)
64
82
Third harmonic and
higher harmonics
Single-ended input (see Note 9)
77
Differential input (see Note 9)
64
77
Single-ended output
(buffered DAC VMID)
(buffered DAC VMID)
(see Note 10)
82
dB
Second harmonic
DAC channel
attenuation
Differential output (see Note 10)
64
82
Third harmonic and
higher harmonics
Single-ended output
(see Note 10)
77
Differential output (see Note 10)
64
77
All typical values are at VDD = 5 V and TA = 25
°
C.
NOTES:
9. The input signal is a 1020-Hz sine wave for the ADC channel. Harmonic distortion is defined for an input
level of –1 dB.
10. The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the
DAC output buffer is 600
from OUT+ to OUT–. Harmonic distortion is specified for a signal input level
of 0 dB.
相關(guān)PDF資料
PDF描述
TLC320AD50(中文) Sigma-Delta Analog Interface Circuit With Master-Slave Function(Sigma-Delta 模擬接口具主從功能)
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