參數(shù)資料
型號(hào): TAS5036APFCRG4
廠商: Texas Instruments, Inc.
英文描述: Six Channel Digital Audio PWM Processor
中文描述: 六通道數(shù)字音頻PWM處理器
文件頁(yè)數(shù): 27/62頁(yè)
文件大?。?/td> 790K
代理商: TAS5036APFCRG4
Architecture Overview
21
SLES061B—November 2002—Revised January 2004
TAS5036A
2.4.1 Clipping Indicator
The clipping output is designed to indicate clipping. When any of the six PWM outputs exceeds the maximum
allowable amplitude, the clipping indicator is asserted. The clipping indicator is cleared every 10 ms.
2.4.2 Error Recovery
Error recovery is used to provide error management and to permit the PWM output to be reset while preserving
all intervolume, interchannel delay, dc offsets, and the other internal settings. Error recovery is initiated by
bringing the ERR_RCVRY terminal low for a minimum 5 MCLK_IN cycles or by setting the error recovery bit
in control register 1. Error recovery is a level-sensitive signal.
The device also performs an error recovery automatically:
When the speed configuration is changed to normal, double, or quad speed
Following a change in the serial data bus interface configuration
When ERR_RCVRY is brought low, all valid signals go low, and the PWM_P and PWM_M outputs go low. If
there are any pending speed configurations, these changes are then performed. When ERR_RCVRY is
brought high, a delay of 4 ms to 5 ms is performed before the system starts the output re-initialization
sequence. After the initialization time, the TAS5036A begins normal operation. During error recovery, all
controls and device settings that were not updated are maintained in their current configurations.
To permit error recovery to be used to provide TAS5100 error management and recovery, the delay between
the start of (falling edge) error recovery and the falling edge of valid 1 though valid 6 is selectable. This delay
can be selected to be either 6
μ
s or 47
μ
s.
During error recovery all serial data bus operations are ignored. At the conclusion of the sequence, the error
recovery register bit is returned to the normal operation state. Table 211 shows the device output signal
states during error recovery.
Table 211. Device Outputs During Error Recovery
SIGNAL
MODE
SIGNAL STATE
Valid 1Valid 6
All
Low
PWM_P outputs
All
Low
PWM_M outputs
All
Low
MCLK_OUT
All
Low
SCLK
Master
Low
SCLK
Slave
Signal input
LRCLK
Master
Low
LRCLK
Slave
Signal input
SDA
All
Signal input
CLIP
All
High
The transitions are done using a quiet entrance and exit sequence to prevent pops and clicks.
2.4.3 Individual Channel Error Recovery
Individual channel error recovery is used to provide error management and to permit the PWM output to be
turned off. Error recovery is initiated by setting one or more of the six error recovery bits in the error recovery
register to low.
While the error recover bits are brought low, the valid signals go to the low state. When the error recovery bits
are brought high, a delay of 4 ms to 5 ms occurs before the channels are returned to normal operation.
The delay between the falling edge of the error recover bit and the falling edge of valid 1 though valid 6 is
selectable. This delay can be selected to be either 6
μ
s or 47
μ
s.
The TAS5036A controls the relative timing of the pseudo-differential drive control signals plus the valid signal
to minimize the production of system noise during error recovery operations. The transitions to valid low and
valid high are done using an almost quiet entrance and exit sequence to prevent pops and clicks.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TAS5036B 制造商:TI 制造商全稱:Texas Instruments 功能描述:Six Channel Digital Audio PWM Precessor
TAS5036B_06 制造商:TI 制造商全稱:Texas Instruments 功能描述:Six Channel Digital Audio PWM Processor
TAS5036BPFC 功能描述:音頻 DSP Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS5036BPFCG4 功能描述:音頻 DSP Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS5036BPFCR 功能描述:多媒體雜項(xiàng) Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 類型: 通道數(shù)量: 轉(zhuǎn)換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube