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參數(shù)資料
| 型號： | TAS5036APFCRG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Six Channel Digital Audio PWM Processor |
| 中文描述： | 六通道數(shù)字音頻PWM處理器 |
| 文件頁數(shù)： | 17/62頁 |
| 文件大?。?/td> | 790K |
| 代理商： | TAS5036APFCRG4 |
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Architecture Overview
11
SLES061B—November 2002—Revised January 2004
TAS5036A
2.1.6 DCLK
DCLK is the internal high-frequency clock that is produced by the PLL circuitry from MCLK. The TAS5036A
uses the DCLK to control all internal operations. DCLK is 8 times the speed of MCLK in normal speed mode,
4 times MCLK in double speed, and 2 times MCLK in quad speed. With respect to the I
2
C addressable
registers, DCLK clock cycles are used to specify interchannel delay and to detect when the MCLK frequency
is drifting. Table 24 DCLK shows the relationship between sample rate, MCLK, and DCLK.
Table 24. DCLK
Fs
(kHz)
MCLK
(MHz)
DCLK
(MHz)
DCLK Period
(ns)
32
8.1920
65.5360
15.3
44.1
11.2896
90.3168
11.1
48
12.2880
98.3040
10.2
88
22.5280
90.1120
11.1
96
24.5760
98.3040
10.2
192
49.1520
98.3040
10.2
2.1.7 Serial Data Interface
The TAS5036A operates as a slave only/receive only serial data interface in all modes. The TAS5036A has
three PCM serial data interfaces to accept six channels of digital data though the SDIN1, SDIN2, SDIN3 inputs.
The serial audio data is in MSB-first, 2s-complement format.
The serial data interfaces of the TAS5036A can be configured in right-justified, I
2
S, left-justified, or DSP
modes. This interface supports 32-kHz, 44.1-kHz, 48-kHz, 88-kHz, 96-kHz, 176.4-kHz, and 192-kHz data
sample rates. The serial data interface format is specified using the data interface control register. The
supported word lengths are shown in Table 25.
During normal operating conditions if the serial data interface settings change state, an error recovery
sequence is initiated.
Table 25. Supported Word Lengths
DATA MODES
WORD
LENGTHS
MOD2
MOD1
MOD0
Right justified, MSB first
16
0
0
0
Right justified, MSB first
20
0
0
1
Right justified, MSB first
I2S
I2S
I2S
24
0
1
0
16
0
1
1
20
1
0
0
24
1
0
1
Left justified, MSB first
24
1
1
0
DSP frame
16
1
1
1
2.1.7.1
I
2
S Timing
I
2
S timing uses LRCLK to define when the data being transmitted is for the left channel or the right channel.
LRCLK is low for the left channel and high for the right channel. A bit clock running at 48 or 64 times Fs is used
to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first
bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS5036A masks unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock.
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PDF描述 |
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| TAS5036B_06 | Six Channel Digital Audio PWM Processor |
| TAS5036BPFCG4 | Six Channel Digital Audio PWM Processor |
| TAS5036BPFCR | Six Channel Digital Audio PWM Processor |
| TAS5036BPFCRG4 | Six Channel Digital Audio PWM Processor |
| TAS5100ADAP | Single Audio Amplifier |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TAS5036B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Six Channel Digital Audio PWM Precessor |
| TAS5036B_06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Six Channel Digital Audio PWM Processor |
| TAS5036BPFC | 功能描述:音頻 DSP Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS5036BPFCG4 | 功能描述:音頻 DSP Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS5036BPFCR | 功能描述:多媒體雜項 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 類型: 通道數(shù)量: 轉換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube |
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