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Introduction
5
SLES061B—November 2002—Revised January 2004
TAS5036A
TERMINAL
FUNCTION
DESCRIPTION
NAME
NO.
PLL_FLT_RET
6
O
PLL external filter (internally connected to AVSS_PLL)
PWM_AM_1
74
O
PWM 1 output (differential -); {positive H-bridge side}
PWM_AM_2
69
O
PWM 2 output (differential -); {positive H-bridge side}
PWM_AM_3
64
O
PWM 3 output (differential -); {positive H-bridge side}
PWM_AM_4
54
O
PWM 4 output (differential -); {positive H-bridge side}
PWM_AM_5
49
O
PWM 5 output (differential -); {positive H-bridge side}
PWM_AM_6
44
O
PWM 6 output (differential -); {positive H-bridge side}
PWM_AP_1
75
O
PWM 1 output (differential +); {positive H-bridge side}
PWM_AP_2
70
O
PWM 2 output (differential +); {positive H-bridge side}
PWM_AP_3
65
O
PWM 3 output (differential +); {positive H-bridge side}
PWM_AP_4
55
O
PWM 4 output (differential +); {positive H-bridge side}
PWM_AP_5
50
O
PWM 5 output (differential +); {positive H-bridge side}
PWM_AP_6
45
O
PWM 6 output (differential +); {positive H-bridge side}
PWM_BM_1
72
O
PWM 1 output (differential -); {negative H-bridge side}
PWM_BM_2
67
O
PWM 2 output (differential -); {negative H-bridge side}
PWM_BM_3
62
O
PWM 3 output (differential -); {negative H-bridge side}
PWM_BM_4
52
O
PWM 4 output (differential -); {negative H-bridge side}
PWM_BM_5
47
O
PWM 5 output (differential -); {negative H-bridge side}
PWM_BM_6
42
O
PWM 6 output (differential -); {negative H-bridge side}
PWM_BP_1
71
O
PWM 1 output (differential +); {negative H-bridge side}
PWM_BP_2
66
O
PWM 2 output (differential +); {negative H-bridge side}
PWM_BP_3
61
O
PWM 3 output (differential +); {negative H-bridge side}
PWM_BP_4
51
O
PWM 4 output (differential +); {negative H-bridge side}
PWM_BP_5
46
O
PWM 5 output (differential +); {negative H-bridge side}
PWM_BP_6
41
O
PWM 6 output (differential +); {negative H-bridge side}
RESET
12
I
System reset input, active low
I2C serial control clock input
SCL
17
I
SCLK
30
I/O
Serial audio data clock (shift clock)
I2C serial control data input/ output
SDA
16
I/O
SDIN1
26
I
Serial audio data 1 input
SDIN2
27
I
Serial audio data 2 input
SDIN3
28
I
Serial audio data 3 input
VALID_1
73
O
Output indicating validity of PWM outputs, channel 1, active high
VALID_2
68
O
Output indicating validity of PWM outputs, channel 2, active high
VALID_3
63
O
Output indicating validity of PWM outputs, channel 3, active high
VALID_4
53
O
Output indicating validity of PWM outputs, channel 4, active high
VALID_5
48
O
Output indicating validity of PWM outputs, channel 5, active high
VALID_6
43
O
Output indicating validity of PWM outputs, channel 6, active high
VREGA_CAP
9
P
Voltage regulator capacitor
VREGB_CAP
60
P
Voltage regulator capacitor
VREGC_CAP
34
P
Voltage regulator capacitor
XTL_IN
79
I
Crystal or TTL level clock input
XTL_OUT
78
O
Crystal output (not for external usage)
I = input; O = output; I/O = input/output; P = power