參數(shù)資料
型號(hào)： TAS5028APAGRG4
廠商： Texas Instruments, Inc.
英文描述： 8 Channel Digital Audio PWM Processor
中文描述： 8通道數(shù)字音頻PWM處理器
文件頁(yè)數(shù)： 16/82頁(yè)
文件大?。?/td> 1226K
代理商： TAS5028APAGRG4
Introduction
8
SLES112 — June 2004
TAS5028A
TERMINAL
DESCRIPTION
ATION
5-V
TOLERANT
I/O
NO.
63
TERMIN-
NAME
MCLK
DI
5 V
Pulldown
MCLK is a 3.3-V clock master clock input. The input frequency of this clock can
range from 4 MHz to 50 MHz.
64
RESERVED
1. Type: A = analog; D = 3.3-V digital; P = power / ground / decoupling; I = input; O = output
2. All pullups are 20-
μ
A weak pullups and all pulldowns are 20-
μ
A weak pull downs. The pullups and pulldowns are included to assure
proper input logic levels if the terminals are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). Devices that drive
inputs with pull ups must be able to sink 20
μ
A, while maintaining a logic 0 drive level. Devices that drive inputs with pulldowns must
be able to source 20
μ
A, while maintaining a logic ‘1’ drive level.
3. If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provide an extended high frequency supply decoupling. This approach avoids the potential of producing
parallel resonance circuits that have been observed when paralleling capacitors of different values.
4. 13.5-MHz crystal (HCM49)
Connect to digital ground
NOTES:
1.4
TAS5028A Functional Description
Figure 1
4 shows the TAS5028A functional structure. The next sections describe the TAS5028A functional
blocks:
Power Supply
Clock, PLL, and Serial Data Interface
Serial Control Interface
Device Control
Digital Audio Processor (DAP)
Pulse Width Modulation (PWM) Processor
1.4.1 Power Supply
The power supply section contains supply regulators that provide analog and digital regulated power for
various sections of the TAS5028A. The analog supply supports the analog PLL, while digital supplies support
the digital PLL, the digital audio processor (DAP), the pulse width modulator (PWM), and the output control
(reclocker). The regulators can also be turned off when terminals RESET and PDN are both low.
1.4.2 Clock, PLL, and Serial Data Interface
The TAS5028A is a clock slave only device and it requires the use of an external 13.5 MHz crystal. It accepts
MCLK, SCLK, and LRCLK as inputs only.
The TAS5028A uses the external crystal to provide a time base for:
Continuous data and clock error detection and management
Automatic data rate detection and configuration
Automatic MCLK rate detection and configuration (automatic bank switching)
Supporting I
2
C operation/ communication while MCLK is absent
The TAS5028A automatically handles clock errors, data rate changes, and master clock frequency changes
without requiring intervention from an external system controller. This feature significantly reduces system
complexity and design.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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TAS5028PAGR 功能描述:音頻 DSP 8 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS5028PAGRG4 功能描述:音頻 DSP 8 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
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