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參數(shù)資料
| 型號(hào)： | STPCD01 |
| 英文描述： | STPC CLIENT DATASHEET / PC COMPATIBLE EMBEDED MICROPROCESSOR |
| 中文描述： | STPC客戶部件/ PC兼容的嵌入式微處理器 |
| 文件頁數(shù)： | 45/61頁 |
| 文件大?。?/td> | 1007K |
| 代理商： | STPCD01 |
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ELECTRICAL SPECIFICATIONS
Issue 2.2 - October 13, 2000
45/61
38l
4
SA[19:0] SBHE valid to IOCHRDY negated
41a
4
Memory access to 16 bit ISA Slave
41b
4
Memory access to 8 bit ISA Slave
41c
4
I/O access to 16 bit ISA Slave
41d
4
I/O access to 8 bit ISA Slave
SA[19:0] SBHE valid to read data valid
42b
4
Memory access to 16 bit ISA Slave Standard cycle
42e
4
Memory access to 8 bit ISA Slave Standard cycle
42h
4
I/O access to 16 bit ISA Slave Standard cycle
42l
4
I/O access to 8 bit ISA Slave Standard cycle
MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW# asserted to IOCHRDY negated
47a
4
Memory access to 16 bit ISA Slave
47b
4
Memory access to 8 bit ISA Slave
47c
4
I/O access to 16 bit ISA Slave
47d
4
I/O access to 8 bit ISA Slave
MEMR#, SMEMR#, IOR# asserted to read data valid
48b
4
Memory access to 16 bit ISA Slave Standard Cycle
48e
4
Memory access to 8 bit ISA Slave Standard Cycle
48h
4
I/O access to 16 bit ISA Slave Standard Cycle
48l
4
I/O access to 8 bit ISA Slave Standard Cycle
IOCHRDY asserted to read data valid
54a
4
Memory access to 16 bit ISA Slave
54b
4
Memory access to 8 bit ISA Slave
54c
4
I/O access to 16 bit ISA Slave
54d
4
I/O access to 8 bit ISA Slave
IOCHRDY asserted to MEMR#, MEMW#, SMEMR#,
SMEMW#, IOR#, IOW# negated
IOCHRY asserted to MEMR#, SMEMR# negated (refresh)
IOCHRDY asserted to next ALE# asserted
IOCHRDY asserted to SA[19:0], SBHE invalid
MEMR#, IOR#, SMEMR# negated to read data invalid
MEMR#, IOR#, SMEMR# negated to daabus float
Write data before MEMW# asserted
61a
4
Memory access to 16 bit ISA Slave
Memory access to 8 bit ISA Slave (Byte copy at end of
start)
Write data before SMEMW# asserted
61c
4
Memory access to 16 bit ISA Slave
61d
4
Memory access to 8 bit ISA Slave
Write Data valid before IOW# asserted
61e
4
I/O access to 16 bit ISA Slave
61f
4
I/O access to 8 bit ISA Slave
MEMW# negated to write data invalid - 16 bit
MEMW# negated to write data invalid - 8 bit
Note; The signal numbering refers to
Table 4-10
Note 4; These timings are extracted from simulations and are not garanteed by testing
I/O access to 8 bit ISA Slave Standard Cycle
10T
Cycles
41
4
6T
12T
6T
12T
Cycles
Cycles
Cycles
Cycles
42
4
4T
10T
4T
10T
Cycles
Cycles
Cycles
Cycles
47
4
2T
5T
2T
5T
Cycles
Cycles
Cycles
Cycles
48
4
2T
5T
2T
5T
Cycles
Cycles
Cycles
Cycles
54
4
1T(R)/2T(W)
1T(R)/2T(W)
1T(R)/2T(W)
1T(R)/2T(W)
Cycles
Cycles
Cycles
Cycles
55a
4
1T
Cycles
55b
4
56
4
57
4
58
4
59
4
61
4
1T
2T
2T
0T
0T
Cycles
Cycles
Cycles
Cycles
Cycles
2T
Cycles
61b
4
2T
Cycles
61
4
2T
2T
Cycles
Cycles
61
4
2T
2T
1T
1T
Cycles
Cycles
Cycles
Cycles
64a
4
64b
4
Table 4-8. ISA Bus AC Timing
Name
Parameter
Min
Max
Units
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STPCD0110BTC3 | 32-Bit Microprocessor |
| STPCD0112BTC3 | 32-Bit Microprocessor |
| STPCD0113BTC3 | 32-Bit Microprocessor |
| STPCI01 | STPC INDUSTRIAL / PC COMPATIBLE EMBEDED MICROPROCESSOR |
| STPCI2 | STPC ATLAS DATASHEET / X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STPCD0110BTC3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| STPCD0112BTC3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| STPCD0113BTC3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| STPCD0166BTA3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PC Compatible Embedded Microprocessor |
| STPCD0166BTC3 | 制造商:STMicroelectronics 功能描述:MPU STPC RISC 64-Bit 66MHz 388-Pin BGA |
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