
UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER
Issue 2.2 - October 13, 2000
25/61
2.3 UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER
The following changes have been made to the Pin Description Chapter on 11/02/2000
The following changes have been made to the Pin Description Chapter on 08/02/2000
The following changes have been made to the Pin Description Chapter on 13/01/2000
DCLK
Dot Clock / Pixel clock. This clock supplies the display controller, the video pipeline, the ramdac,
and the TV output logic. Its value is dependent on the selected display mode.
Its frequency can be as high as 135 MHz. This signal is either driven by the internal PLL to a minimum of
8MHz or by an external oscillator. The direction can be controlled by a strap option or an internal register
bit.
The following changes have been made to the Pin Description Chapter on 28/09/99
The following changes have been made to the Pin Description Chapter on 23/09/99
The following changes have been made to the Pin Description Chapter on 11/08/99
Section
Change
Text
“
Signals AD[12:11] for internal use only. Not to be used for External PCI devic-
es.”
2.2.5.
Added
Section
2.2.3.
Change
Replaced
Text
Signals VIDEO_D[7:0] with VIN, VTV_BT# with ODD_EVEN, VTV_SYNCH with VCS.
Section
2.2.
Change
Added
Text
“
to a minimum of 8MHz”
Section
Table 2-1.
Changed
Figure 2-1.
Changed
Table 2-2.
Replaced
2.2.1.
2.2.1.
2.2.3.
Change
Text
Updated signal pin counts and added abbreviations to table.
Updated External interface pin count
“PWGD” with “SYSRSTI#”
PCI_CLKI and PCI_CLKO moved from
2.2.1.
to
2.2.5.
ISA_CLK and ISA_CLKX2 moved from
2.2.1.
to
2.2.8.
“Video Interface” with “Video Input”
Moved
Moved
Replaced