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參數(shù)資料
| 型號： | STPCD01 |
| 英文描述： | STPC CLIENT DATASHEET / PC COMPATIBLE EMBEDED MICROPROCESSOR |
| 中文描述： | STPC客戶部件/ PC兼容的嵌入式微處理器 |
| 文件頁數(shù)： | 18/61頁 |
| 文件大小： | 1007K |
| 代理商： | STPCD01 |
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PIN DESCRIPTION
18/61
Issue 2.2 - October 13, 2000
2.2.8.
ISA CONTROL
SYSRSTO#
Reset Output to System. This is the
system reset signal and is used to reset the rest of
the components (not on Host Bus) in the system.
The ISA bus reset is an externally inverted buff-
ered version of this output and the PCI bus reset is
an externally buffered version of this output.
ISA_CLK
ISA Clock Output (also Multiplexer Se-
lect Line For IPC). This pin produces the Clock
signal for the ISA bus. It is also used with
ISA_CLK2X as the multiplexor control lines for the
Interrupt Controller Interrupt input lines. This is a
divided down version of either the PCICLK or
OSC14M.
ISA_CLKX2
ISA Clock Output (also Multiplexer
Select Line For IPC). This pin produces a signal at
twice the frequency of the Clock signal for the ISA
bus. It is also used with ISA_CLK as the multiplex-
or control lines for the Interrupt Controller Interrupt
input lines.
OSC14M
ISA Bus Synchronization Clock Output.
This is the buffered 14.318 Mhz clock to the ISA
bus.
ALE
Address Latch Enable. This is the address
latch enable output of the ISA bus and is asserted
by the STPC Client to indicate that LA23-17,
SA19-0, AEN and SBHE# signals are valid. The
ALE is driven high during refresh, DMA master or
ISA master cycles by the STPC Client.
ALE is driven low after reset.
BHE#
System Bus High Enable. This signal, when
asserted, indicates that a data Byte is being trans-
ferred on SD15-8 lines. It is used as an input when
an ISA master owns the bus and is an output at all
other times.
MEMR#
Memory Read. This is the memory read
command signal of the ISA bus. It is used as an in-
put when an ISA master owns the bus and is an
output at all other times.
The MEMR# signal is active during refresh.
MEMW#
Memory Write. This is the memory write
command signal of the ISA bus. It is used as an in-
put when an ISA master owns the bus and is an
output at all other times.
SMEMR#
System Memory Read. The STPC Cli-
ent generates SMEMR# signal of the ISA bus only
when the address is below 1MByte or the cycle is
a refresh cycle.
SMEMW#
System Memory Write. The STPC Cli-
ent generates SMEMW# signal of the ISA bus
only when the address is below 1MByte.
IOR#
I/O Read. This is the I/O read command sig-
nal of the ISA bus. It is an input when an ISA mas-
ter owns the bus and is an output at all other
times.
IOW#
I/O Write. This is the I/O write command sig-
nal of the ISA bus. It is an input when an ISA mas-
ter owns the bus and is an output at all other
times.
MASTER#
Add On Card Owns Bus. This signal is
active when an ISA device has been granted bus
ownership.
MCS16#
Memory Chip Select 16. This is the de-
code of LA23-17 address pins of the ISA address
bus without any qualification of the command sig-
nal lines. MCS16# is always an input. The STPC
Client ignores this signal during I/O and refresh
cycles.
IOCS16#
I/O Chip Select 16. This signal is the de-
code of SA15-0 address pins of the ISA address
bus without any qualification of the command sig-
nals. The STPC Client does not drive IOCS16#
(similar to PC-AT design). An ISA master access
to an internal register of the STPC Client is exe-
cuted as an extended 8-bit I/O cycle.
REF#
Refresh Cycle. This is the refresh command
signal of the ISA bus. It is driven as an output
when the STPC Client performs a refresh cycle on
the ISA bus. It is used as an input when an ISA
master owns the bus and is used to trigger a re-
fresh cycle.
The STPC Client performs a pseudo hidden re-
fresh. It requests the host bus for two host clocks
to drive the refresh address and capture it in exter-
nal buffers. The host bus is then relinquished
while the refresh cycle continues on the ISA bus.
AEN
Address Enable. Address Enable is enabled
when the DMA controller is the bus owner to indi-
cate that a DMA transfer will occur. The enabling
of the signal indicates to I/O devices to ignore the
IOR#/IOW# signal during DMA transfers.
IOCHCK#
I/O Channel Check. /O Channel Check
is enabled by any ISA device to signal an error
condition that can not be corrected. NMI signal be-
comes active upon seeing IOCHCK# active if the
corresponding bit in Port B is enabled.
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