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參數(shù)資料
| 型號： | STLS2F02-LP |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, PBGA452 |
| 封裝： | 27 X 27 MM, 2.90 MM HEIGHT, ROHS COMPLIANT, HFCBGA-452 |
| 文件頁數(shù)： | 9/49頁 |
| 文件大小： | 706K |
| 代理商： | STLS2F02-LP |
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STLS2F02-LP
IO bus interface description
3
IO bus interface description
The STLS2F02-LP processor IO interface consists of the PCI bus and a local bus. The PCI
bus is used to for generic peripheral device interface, while the local bus a simple interface
for processor boot or debug.
3.1
PCI interface characteristic
The PCI interface features are as follows:
●
PCI 2.3 and PCIX 1.0 compatible
●
Support PCI 66 MHz and PCIX133 MHz
●
Support dual address cycle for 64-bit addressing
●
Support 8 outstanding master request in PCIX mode
●
Support 4 delay-split read request in PCIX mode
3.2
Host and agent mode
The STLS2F02-LP PCI interface can work in host mode or agent mode, depending on the
initial value of signal PCI_CONFIG.
When the processor works in host mode, the interface initializes the bus device according to
the value of PCI_CONFIG[6:4]. In this case, PCI_IDSEL can be connected directly to GND.
When the processor works in agent mode, the initial value of the PCI bus defines the
working-mode of the interface. In host mode, on the system main board, the value of
PCI_CONFIG[6:4] should be set according to the ability of bus device. (Refer also to the
PCIX 1.0 standard)
3.3
PCI bus arbitrator
The PCI/PCIX bus arbitrator built into the STLS2F02-LP supports up t o 7 external masters.
The arbitration rules are two-level round robin scheduling. The level of each request is
determined by software configuration. The bus is granted to insert a dummy cycle during
switching. Bus parking can be configured as the last master or any specified master.
The internal request/grant wire of the interface can be set to connect to the number 0
request/grant wire by PCI_CONFIG [1] so that the external bus arbitrator can be used.
3.4
System interface connection
The STLS2F02-LP processor can be easily implemented in uniprocessor system. Since no
multi-processor cache coherence protocol is supported in the PCI interface, the cache
coherence should be managed by software in a multiprocessor system.
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