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參數(shù)資料
| 型號： | STLS2F02-LP |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, PBGA452 |
| 封裝： | 27 X 27 MM, 2.90 MM HEIGHT, ROHS COMPLIANT, HFCBGA-452 |
| 文件頁數(shù)： | 5/49頁 |
| 文件大?。?/td> | 706K |
| 代理商： | STLS2F02-LP |
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STLS2F02-LP
Interface description
2.6
Interrupt signals
The STLS2F02-LP processor supports up to 12 external interrupts and one non-maskable
interrupt (NMI). There are 4 PCI interrupt signals, 4 special interrupt signals and 4
configurable GPIO interrupt. There are also 3 internal interrupts, two PCI bus error report
signals and one DDR2 control interrupt. When an interrupt occurs, the processor handles
the exception. Table 6 details the interrupt signals.
2.7
JTAG signals
The STLS2F02-LP provides a JTAG-compliant boundary scan interface. The JTAG interface
is particularly suitable for testing the processor pins for connectivity. Table 7 details the JTAG
signals.
2.8
Test and control signals
On the STLS2F02-LP chip, the test signals are only used for chip physical test, for example
scan chain test. When the chip works normally, these signals are set invalid (to 1).
Table 6.
Interrupt interface signals
Name
Input/output
Description
INTn[3:0]
I
4 external interrupt signals. OR operations are performed
on these signals with interrupt register from bit 5 to bit 2
separately
NMIn
I
NMI. An OR operation is performed on the NOT-value of
this signal and the interrupt register’s 6th bit
GPIO[3:0]
I/O
These interrupts should be enabled in the interrupt
controller and can be configured as different active power
level and different trigger mode. These interrupts could be
routed to interrupt register bit 0/1
PCI_IRQ[3:0]
I
These interrupts should be enabled in the interrupt
controller and low active. These interrupts could be routed
to interrupt register bit 0/1
PCI_PERR
I/O
PCI bus parity error, high pulse active. These interrupts
could be routed to interrupt register bit 0/1
PCI_SERR
I/O
PCI bus error, high pulse active. These interrupts could be
routed to interrupt register bit 0/1
Table 7.
JTAG interface signals
Name
Input/output
Description
TDI
I
JTAG serial scan data input
TDO
O
JTAG serial scan data input
TMS
I
JTAG command, indicating that the input serial data is a
command.
TCK
I
JTAG serial scan clock
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