參數(shù)資料
型號(hào)： STLS2F02-LP
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, PBGA452
封裝： 27 X 27 MM, 2.90 MM HEIGHT, ROHS COMPLIANT, HFCBGA-452
文件頁(yè)數(shù)： 14/49頁(yè)
文件大小： 706K
代理商： STLS2F02-LP
STLS2F02-LP
DDR2 SDRAM controller interface description
4
DDR2 SDRAM controller interface description
The STLS2F02-LP integrates a built-in memory controller compliant with DDR2 SDRAM
standard (JESD79-2B). The STLS2F02-LP provides JESD79-2B-compliant read/write
memory operations.
4.1
DDR2 SDRAM controller features
The STLS2F01 CPU supports up to 4 physical memories by using two DDR SDRAM chip
select signals, with an 18-bit address bus (15-bit row/column address and 3-bit logic bank
bus). The maximum address space is 128 Gbytes (237 bytes).
This device supports all the JESD79-2B-compatible memory chips. The DDR2 controller
parameters can be set to support specific memory chip type. The maximum number of chip
selection (CS_n) is 2-bit. The maximum width of row address (RAS_n) is 15-bit, and the
maximum width of column address (CAS_n) is 14-bit. And there is 3-bit logic bank bus
(BANK_n).
For example, in the 4 Gbyte address space configuration of 2-bit CS_n, 3-bit BANK_n,
12-bit RAS_n and 12-bit CAS_n, the physical memory address CPU required can be
translated into row/column address as shown in Figure : .
Figure 7.
DDR2 SDRAM row/column address translation
The built-in memory controller IC receives only memory read/write requests from a
processor or external device. The controller IC is in slave state whenever memory are read
or written.
A dynamic page management policy is implemented on the integrated memory controller.
For one access to memory, the controller selects open page/close page strategies on a
hardware circuit, without software designers’ intervention. The memory controller features:
●
Full pipelining support to command and read/write data of interface
●
Increasing bandwidth by merging and sorting memory command
●
Modify fundamental parameters through the configuration of register read/write ports
●
Built-in delay compensation circuit (DCC), it is used to send/receive data reliably
●
1-bit and 2-bit error detection, 1-bit error correction by error correcting-code (ECC)
●
Frequency: 133 MHz to 333 MHz.
36
32 31
30 29
18 17
15 14
3 2
0
CS_n
RAS_n
BANK_n
CAS_n
Byte_enable
52
12
3
12
3
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