參數(shù)資料
型號(hào)： ST72521BAR9
英文描述： ST72521B - 80/64-PIN 8-BIT MCU WITH 32 TO 60K ROM. FIVE TIMERS. SPI. SCI. I2C. CAN INTERFACE
中文描述： ST72521B - 80/64-PIN 8位32至60,000 ROM的微處理器。 5個(gè)定時(shí)器。的SPI。脊髓損傷。 I2C總線。 CAN接口
文件頁(yè)數(shù)： 56/198頁(yè)
文件大?。?/td> 2504K
代理商： ST72521BAR9
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ST72521B
56/198
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK
(Cont’d)
9.2.5 Low Power Modes
9.2.6 Interrupts
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
Note
:
The MCC/RTC interrupt wakes up the MCU from
ACTIVE-HALT mode, not from HALT mode.
9.2.7 Register Description
MCC CONTROL/STATUS REGISTER (MCCSR)
Read/Write
Reset Value: 0000 0000 (00h
)
Bit 7 =
MCO
Main clock out selection
This bit enables the MCO alternate function on the
PF0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: MCO alternate function enabled (f
CPU
on I/O
port)
Note
: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.
Bit 6:5 =
CP[1:0]
CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
Bit 4 =
SMS
Slow mode select
This bit is set and cleared by software.
0: Normal mode. f
CPU
=
f
1: Slow mode. f
CPU
is given by CP1, CP0
See
Section 7.2 SLOW MODE
and
Section 9.2
MAIN CLOCK CONTROLLER WITH REAL TIME
CLOCK AND BEEPER (MCC/RTC)
for more de-
tails.
Bit 3:2 =
TB[1:0]
Time base control
These bits select the programmable divider time
base. They are set and cleared by software.
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
Bit 1 =
OIE
Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVE-
HALT mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode
.
Mode
Description
WAIT
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.
No effect on MCC/RTC counter (OIE bit is
set), the registers are frozen.
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit
from HALT” capability.
ACTIVE-
HALT
HALT
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Time base overflow
event
OIF
OIE
Yes
No
1)
7
0
MCO
CP1
CP0
SMS
TB1
TB0
OIE
OIF
f
CPU
in SLOW mode
f
OSC2
/ 2
f
OSC2
/ 4
f
OSC2
/ 8
f
OSC2
/ 16
CP1
CP0
0
0
1
1
0
1
0
1
Counter
Prescaler
Time Base
TB1
TB0
f
OSC2
=4MHz f
OSC2
=8MHz
4ms
8ms
20ms
50ms
16000
32000
80000
200000
2ms
4ms
10ms
25ms
0
0
1
1
0
1
0
1
相關(guān)PDF資料
PDF描述
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ST72521BR6 ST72521B - 80/64-PIN 8-BIT MCU WITH 32 TO 60K ROM. FIVE TIMERS. SPI. SCI. I2C. CAN INTERFACE
ST72521BR9 ST72521B - 80/64-PIN 8-BIT MCU WITH 32 TO 60K ROM. FIVE TIMERS. SPI. SCI. I2C. CAN INTERFACE
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