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參數(shù)資料
| 型號： | ST72521BAR9 |
| 英文描述： | ST72521B - 80/64-PIN 8-BIT MCU WITH 32 TO 60K ROM. FIVE TIMERS. SPI. SCI. I2C. CAN INTERFACE |
| 中文描述： | ST72521B - 80/64-PIN 8位32至60,000 ROM的微處理器。 5個定時器。的SPI。脊髓損傷。 I2C總線。 CAN接口 |
| 文件頁數(shù)： | 169/198頁 |
| 文件大?。?/td> | 2504K |
| 代理商： | ST72521BAR9 |
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ST72521B
169/198
EMC CHARACTERISTICS
(Cont’d)
11.8.3.2 Static and Dynamic Latch-Up
I
LU
: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 ST7 application note.
I
DLU
: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in
Figure 86
. For
more details, refer to the AN1181 ST7
application note.
11.8.3.3 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
Electrical Sensitivities
Figure 86. Simplified Diagram of the ESD Generator for DLU
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
Symbol
Parameter
Conditions
Class
1)
LU
Static latch-up class
T
A
=
+25°C
T
A
=
+85°C
T
A
=
+125°C
V
DD
=
5.5V, f
OSC
=
4MHz, T
A
=
+25°C
A
A
A
A
DLU
Dynamic latch-up class
R
CH
=50M
R
D
=330
C
S
=
150pF
ESD
GENERATOR
2)
HV RELAY
DISCHARGE TIP
DISCHARGE
RETURN CONNECTION
ST7
V
DD
V
SS
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