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參數(shù)資料
| 型號： | ST70135A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | ASCOTTM DMT TRANSCEIVER |
| 中文描述： | ASCOTTM大唐收發(fā)器 |
| 文件頁數(shù)： | 21/29頁 |
| 文件大小： | 198K |
| 代理商： | ST70135A |
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ST70135A
21/29
BitStream Interface
The Bitstream interface is a proprietary point to
point interface. The ST70135A is the bus master
of the interface. The interface is synchronous, a
common clock is used.
SLAP (Synchronous Link Access Protocol)
Interface
The SLAP interface is a point to point bitstream
interface. The ST70135A is the bus master of the
interface.
The
interface
common clock (SLAP_CLOCK) isused. The basic
idea is illustrated in Figure 17.
The SLAP interface dumps the data of the fast
and interleaved channels on 2 separate sub
interfaces.
The data flow from the SLAP interface must be
enabled by the Transceiver Controller. A disabled
cell interface does not dump data on its interface.
Figure 18 :
Common Clock Data Transfer
is
synchronous,
a
Receive SLAP Interface
The interface signals use 2 signal types: (refer to
Figure 19)
– SLR_DATA [1:0]: data pins,a byte is transferred
in 4 cycles of 2 bits. The msb are transmitted
first, odd bits are asserted on SLR_DATA [1].
– SLR_VAL: indicates the data transfer and the
byte boundary
– SLR_FRAME: indicates the start of a super-
frame
Notice 2 SLAP interfaces are supported, one for
the fast data flow, the other one for the interleaved
data flow.
The logic timing diagram is shown in Figure 20.
Figure 19 :
Receive Path, SLAP Interface
D
Q
CK
QN
Source
Rising
Clock
D
Q
CK
QN
Falling
Clock
Sink
SLAP_CLOCK
EXTERNAL
COMPONENT
(SLAVE)
SLAP_CLOCK
MODEM
(MASTER)
DATA
2
VALID
FRAME
Figure 20 :
Receive SLAP Interface Timing
One byte as 4 times 2 bits
b4
b6
0
1
2
3
8
Minimum 8 cycles
STM_CLOCK
Undefined
Undefined
FRAME
VALID
SLR_VAL must not repeat
in a 8 clock period
b5
b3
b1
b2
b0
b7
SLR_DATA(1)
SLR_DATA(0)
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| ST70136G | CPE ADSL ANALOG FRONT END |
| ST70137 | UNICORNTM PCI & USB CONTROLLERLESS ADSL DMT TRANSCEIVER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST70136 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CPE ADSL ANALOG FRONT END |
| ST70136B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CPE ADSL ANALOG FRONT END |
| ST70136G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CPE ADSL ANALOG FRONT END |
| ST70136Q | 功能描述:射頻無線雜項 ADSL Analg Front-End RoHS:否 制造商:Texas Instruments 工作頻率:112 kHz to 205 kHz 電源電壓-最大:3.6 V 電源電壓-最小:3 V 電源電流:8 mA 最大功率耗散: 工作溫度范圍:- 40 C to + 110 C 封裝 / 箱體:VQFN-48 封裝:Reel |
| ST70137 | 制造商:STMicroelectronics 功能描述: |
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