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參數(shù)資料
| 型號： | ST70135A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | ASCOTTM DMT TRANSCEIVER |
| 中文描述： | ASCOTTM大唐收發(fā)器 |
| 文件頁數(shù)： | 16/29頁 |
| 文件大?。?/td> | 198K |
| 代理商： | ST70135A |
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ST70135A
16/29
Generic Processor Interface Pins and
Functional Description
Digital interface ATM or serial
Digital
before modulation
demodulation.
Interface
for
and
data
from
to
the
loop
loop
after
the
This interface collects cells (from the cell based
function module) or a byte stream (from the
deframer).
Cells are stored in a fifo, 2 interfaces submodules
can extract data from the fifo. Byte streams are
dumped on the bitstream interface (with no fifo).
3 kinds of interface are allowed:
– Utopia Level 1
– Utopia Level 2
– Bitstream based on a proprietary exchange
The interface selection is programmed by writing
the Utopia PHY address register.
Only one interface can be enabled in a ST70135A
configuration.
Utopia Level 1 supports only one PHY device.
Utopia Level 2 supports multi-PHY devices (See
Utopia Level 2 specifications).
Each buffer provides storage for 8 ATM cells(both
directions for Fast and Interleaved channel).
The Utopia Level 2 supports point to multipoint
configurations
by
introducing
capability and by making distinction between
polling and selecting a device.
an
addressing
Figure 12 :
Receive Interface
Utopia Level 1 Interface
The ATM forum takes the ATM layer chip as a
reference. It defines the direction from ATM to
physical layer as the Transmitdirection.
The direction from physical layer to ATM is the
Receive direction. Figures 12 & 13 show the
interconnection between ATM and PHY layer
devices, the optional signals are not supported
and not shown.
The Utopia interface transfers one byte in a single
clock cycle, as a result cells are transformed in 53
clock cycles.
Both transmit and receive are synchronized on
clocks generated by the ATM layer chip, and no
specific relationship between receive and transmit
clocks is required. In this mode, the ST70135A
can only support one data flow : either interleaved
or fast.
Name
Type
Function
AD[0..15]
I/O
Multiplexed address / data bus
ALE
I
Address Latch Enable
RDB
I
Read cycle indication
WRB
I
Write cycle indication
CSB
I
Chip Select
RDYB
OZ
Bus cycle ready indication
INTB
O
Interrupt
Figure 13 :
Transmit Interface
PHY
RECEIVE
RxREF*
RxCLAV
RxENB*
RxCLK
RxDATA
RxSOC
CELL
RECEIVE
PHY
ATM
8
PHY
TRANSMIT
TxREF*
TxCLAV
TxENB*
TxCLK
TxDATA
TxSOC
CELL
TRANSMIT
PHY
ATMLAYER
8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST70136 | CPE ADSL ANALOG FRONT END |
| ST70136B | CPE ADSL ANALOG FRONT END |
| ST70136G | CPE ADSL ANALOG FRONT END |
| ST70137 | UNICORNTM PCI & USB CONTROLLERLESS ADSL DMT TRANSCEIVER |
| ST70137TQFP | UNICORNTM PCI & USB CONTROLLERLESS ADSL DMT TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST70136 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CPE ADSL ANALOG FRONT END |
| ST70136B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CPE ADSL ANALOG FRONT END |
| ST70136G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CPE ADSL ANALOG FRONT END |
| ST70136Q | 功能描述:射頻無線雜項(xiàng) ADSL Analg Front-End RoHS:否 制造商:Texas Instruments 工作頻率:112 kHz to 205 kHz 電源電壓-最大:3.6 V 電源電壓-最小:3 V 電源電流:8 mA 最大功率耗散: 工作溫度范圍:- 40 C to + 110 C 封裝 / 箱體:VQFN-48 封裝:Reel |
| ST70137 | 制造商:STMicroelectronics 功能描述: |
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