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參數(shù)資料
| 型號： | ST62E18C |
| 廠商： | 意法半導體 |
| 英文描述： | 16-Bit Registered Transceivers With 3-State Outputs 56-SSOP -40 to 85 |
| 中文描述： | 8位單片機與微控制器/ D轉換器，自動重加載定時器，UART的秘書長辦公室，安全復位和20管腳封裝 |
| 文件頁數(shù)： | 58/82頁 |
| 文件大小： | 536K |
| 代理商： | ST62E18C |
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ST62T18C/E18C
5.3 INSTRUCTION SET
The ST6 core offers a set of 40 basic instructions
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be di-
vided into six different types: load/store, arithme-
tic/logic, conditional branch, control instructions,
jump/call, and bit manipulation. The following par-
agraphs describe the different types.
All the instructions belonging to a given type are
presented in individual tables.
Load & Store
. These instructions use one, two or
three bytes in relation with the addressing mode.
One operandis the Accumulator for LOAD and the
other operand is obtained fromdata memory using
one of the addressing modes.
For Load Immediate one operand can be any of
the 256 data space bytes while theother is always
immediate data.
Table 20. Load & Store Instructions
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# .
Immediate data (stored in ROM memory)
rr.
Data space register
.
Affected
* .
Not Affected
Instruction
Addressing Mode
Bytes
Cycles
Flags
Z
*
C
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
LD A, X
LD A, Y
LD A, V
LD A, W
LD X, A
LD Y, A
LD V, A
LD W,A
LD A, rr
LD rr, A
LD A, (X)
LD A, (Y)
LD (X), A
LD (Y), A
LDI A, #N
LDI rr, #N
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Direct
Direct
Indirect
Indirect
Indirect
Indirect
Immediate
Immediate
1
1
1
1
1
1
1
1
2
2
1
1
1
1
2
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
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