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參數(shù)資料
| 型號： | ST62E18C |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 16-Bit Registered Transceivers With 3-State Outputs 56-SSOP -40 to 85 |
| 中文描述： | 8位單片機與微控制器/ D轉(zhuǎn)換器，自動重加載定時器，UART的秘書長辦公室，安全復(fù)位和20管腳封裝 |
| 文件頁數(shù)： | 54/82頁 |
| 文件大?。?/td> | 536K |
| 代理商： | ST62E18C |
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ST62T18C/E18C
U. A. R. T
(Cont’d)
4.5.2 Clock Generation
The UART contains a built-in divider of the MCU
internal clock for most common Baud Rates as
shown in Table 19. Other baud rate values can be
calculated from the chosen oscillator frequency di-
vided by the Divisor value shown.
The divided clock provides a frequency that is 8
times the desired baud rate. This allows the Data
reception mechanism to provide a 2 to 1 majority
voting system to determine the logic state of the
asynchronous incoming serial logic bit by taking 3
timed samples within the 8 time states.
The bits not sampled provide a buffer to compen-
sate for frequency offsets between sender and re-
ceiver.
4.5.3 Data Transmission
Whatever the format selected as MCU option, 10-
bit or 11-bit frame, the start and stop bit are auto-
matically generated by the UART. Only the re-
maining 8 (Resp. 9) bit in the 10-bit (Resp. 11-bit)
frame are under control of the user.
Transmission is started by writing the Data Regis-
ter, after having previously set the transmission
software options, the baudrate and the parity ena-
ble. In case of 11-bit frame, the 9th bit must then
be set before into the LSB of the UART Control
Register. Bit 9 remains in the state programmed
for consecutive transmissions until changed by the
user oruntil a character is received when the state
of this bit is changed to that of theincoming bit 9.
The UARTOE signal switches the output multi-
plexer to the UART output and a start bit is sent (a
0 for one bit time) followed by the data bit with the
LSB D0 at first.. The output is then set to 1 for a
period of one bit time to generate a Stop bit, and
then the UARTOE signal returns the TXD1 line to
its alternate I/O function. The end of transmission
is flagged by setting TXMT to 1 and an interrupt is
generated if enabled. The TXMT flag is reset by
writing a 0 to the bit position, it is also cleared au-
tomatically when a new character is written to the
Data Register. TXMT can be set to 1 by software
to generate a software interrupt so care must be
taken in manipulating the Control Register.
4.5.3.1 Character Format
Once the MCU option is set as 10-bit or 11-bit
frame, the frame length is fixed. Within these8 or9
remaining bit, any format can be used as shown in
the Table 18. Only the even parity automatic com-
putation in the 10-bit frame is available. Any other
parity bit can however be software computed and
processed as a data bit
Table 18. Character Options
Figure 31. 11-bit Character Format Example
Figure 32. UART Data Output
10 bit frame
No Parity
1 Even Parity (Auto)
1 Software Parity
11 bit frame
1 Software Parity
No Parity
No Parity
1 Software Parity
Start Bit
Start Bit
Start Bit
8 Data
7 Data
7 Data
1 Stop
1 Stop
1 Stop
Start Bit
Start Bit
Start Bit
Start Bit
8 Data
9 Data
8 Data
7 Data
1 Stop
1 Stop
2 Stop
2 Stop
VR02012
POSITION
1
2
8
10
BIT
BIT
START
STOP
BIT
POSSIBLE
NEXT
CHARACTER
START
D0 D1
D7 D8
START OF DATA
9
TXD1
TXD
PORT DATA
OUTPUT
0
MUX
1
UARTOE
VR02011
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