參數(shù)資料
型號： ST62E18C
廠商： 意法半導(dǎo)體
英文描述： 16-Bit Registered Transceivers With 3-State Outputs 56-SSOP -40 to 85
中文描述： 8位單片機(jī)與微控制器/ D轉(zhuǎn)換器，自動重加載定時器，UART的秘書長辦公室，安全復(fù)位和20管腳封裝
文件頁數(shù)： 5/82頁
文件大?。?/td> 536K
代理商： ST62E18C
5/82
ST62T18C/E18C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T18C and ST62E18C devices are low
cost members of the ST62xx 8-bit HCMOS family
of microcontrollers, which are targeted at low to
medium complexity applications. All ST62xx de-
vices are based on a building block approach: a
common core is surrounded by a number of on-
chip peripherals.
The ST62E18C is theerasable EPROM version of
the ST62T18C device, which may be used to em-
ulate the ST62T18C device, as well asthe respec-
tive ST6218C ROM devices.
Figure 1. Block Diagram
TEST
NMI
INTERRUPT
PROGRAM
Memory
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
POWER
SUPPLY
OSCILLATOR
RESET
DATA ROM
USER
SELECTABLE
DATA RAM
PORT A
PORT B
TIMER
DIGITAL
WATCHDOG
8 BIT CORE
TEST/V
PP
8-BIT
A/D CONVERTER
PA2/ARTIMout / 20 mA Sink
PA3/ARTIMin/ 20 mA Sink
PA4..PA5/20mA Sink
V
DD
V
SS
OSCin OSCout
RESET
AUTORELOAD
TIMER
192 Bytes
7948 bytes
PB4..PB6/Ain
PORT D
PD6,PD7/Ain
PD4/Ain/RXD1
PD5/Ain/TXD1
(VPP on EPROM/OTP versions only)
TIMER
VR01823F
UART
5
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