參數(shù)資料
型號: ST6240B
廠商: 意法半導(dǎo)體
英文描述: Replaced by PT6302 : 5Vout 3A Wide Input Positive Step-Down ISR 3-SIP MODULE -40 to 70
中文描述: 8位檢察官辦公室/存儲器與LCD驅(qū)動器,EEPROM和一個微處理器/ D轉(zhuǎn)換器
文件頁數(shù): 48/76頁
文件大小: 1280K
代理商: ST6240B
48/76
ST62T40B/E40B
4.5 LCD CONTROLLER-DRIVER
On-chip LCD driver includes all features required
for LCD driving, including multiplexing of the com-
mon plates. Multiplexing allows to increase display
capability without increasing the number of seg-
ment outputs. In that case, the display capability is
equal to the product of the number of common
plates with the number of segment outputs.
A dedicated LCD RAM is used to store the pattern
to be displayed while control logic generates ac-
cordingly all the waveforms sent onto the segment
or common outputs. Segments voltage supply is
MCU supply independant, and included driving
stages allow direct connection to the LCD panel.
The multiplexing ratio (Number of common plates)
and the base LCD frame frequency is software
configurable to achieve the best trade-off con-
trast/display capability for each display panel.
The 32Khz clock used for the LCD controller is
derivated from the MCU’s internal clock and there-
fore does not require a dedicated oscillator. The
division factor is set by the three bits HF0..HF2 of
the LCD Mode Control Register LCDCR as sum-
marized in
Table 19
for recommanded oscillator
quartz values. In case of oscillator failure, all seg-
ment and common lines are switched to ground to
avoid any DC biasing of the LCD elements.
Table 19. Oscillator Selection Bits
Notes
:
1.
defined in this table cause the LCD to operate at a
reference frequency different from 32.768kHz, ac-
cording to division factor of
Table 19
.
2.
It is not recommended to select an internal
frequency lower than 32.768kHz as the clock su-
pervisor circuit may switch off the LCD peripheral
if lower frequency is detected.
The usage f
values different from those
Figure 26. LCD Block Diagram
MCU
Oscillator
f
OSC
HF2 HF1 HF0
Division Factor
0
0
1
1
1
0
1
0
0
1
0
1
0
1
0
Clock disabled: Display off
32
64
128
256
1.048MHz
2.097MHz
4.194MHz
8.388MHz
DATA BUS
CONTROL
REGISTER
LCD
RAM
SEGMENT
DRIVER
COMMON
DRIVER
VOLTAGE
DIVIDER
CONTROLLER
CLOCK
SELECTION
VLCD
1/3
VLCD VLCD
2/3
BACKPLANES
SEGMENTS
f
int
OSC 32kHz
(When available)
VR02099
32kHz
620
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