參數(shù)資料
型號: ST52514K3
英文描述: IC MAX 7000 CPLD 256 100-TQFP
中文描述: 8位重癥監(jiān)護(hù)病房,10位ADC。兩個定時器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存
文件頁數(shù): 49/106頁
文件大小: 1355K
代理商: ST52514K3
6.6 Register Description
The following section describes the Register which
are used to configure the Clock, Reset, PLVD and
PHW.
6.6.1 Configuration Register.
CPU Clock Prescaler (CPU_CLK)
Configuration Register 46 (02Eh) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-6: Not Used
Bit 5-0: CPUCK5-0 CPU Clock Prescaler bits
The CPU Clock frequency is divided by a
factor described in the following table
PLVD Control Register (PLVD_CR)
Configuration Register 51 (033h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-2: Not Used
Bit 1-0: PLVDI1-0 PLVD interrupt detection levels
00: PLVD disabled
01: Medium detection level
10: Lowest detection level
11: Highest detection level
Remark: The PLVDI1-0 bits are used only if the
PLVD has been configured to generate a interrupt
(PVDSEL=1
in
PLVD_SET
Option
Byte),
otherwise the PLVDR1-0 of the PLVD_SET Option
Byte are used (see below)
PHW Control Register (PHW_CR)
Configuration Register 52 (034h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7: PHWEN Programmable Halt Wakeup Enable
0: PHW disabled
1: PHW enabled
Bit 6: PHWSEL PHW Action selection
0: PHW generates a Interrupt
1: PHW generates a Reset
Bit 5-0: PHWC5-0 PHW Counter
000000: Counter = 26 ~ 2 ms
000001: Counter = 26 ~ 2 ms
000010: Counter = 28 ~ 8 ms
000100: Counter = 210 ~ 32 ms
001000: Counter = 212 ~ 128 ms
010000: Counter = 214 ~ 512 ms
100000: Counter = 216 ~ 2 s
Note: if more than one bit is set in the PHW
Counter,
only
the
less
significative
will
be
considered. When a new value is latched, the
count restarts.
70
-
CPUCK5 CPUCK4 CPUCK3 CPUCK2 CPUCK1 CPUCK0
CPUCK5-0
CPU Clock
000000
fCPU=fOSC
000001
fCPU=fOSC/2
000010
fCPU=fOSC/4
000100
fCPU=fOSC/8
001000
fCPU=fOSC/16
010000
fCPU=fOSC/32
100000
fCPU=fOSC/64
others
fCPU=fOSC/64
70
--
---
-
PLVDI1
PLVDI0
75
0
PHWEN PHWSEL PHWC5 PHWC4 PHWC3 PHWC2 PHWC1 PHWC0
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