參數(shù)資料
型號(hào)： ST52514K3
英文描述： IC MAX 7000 CPLD 256 100-TQFP
中文描述： 8位重癥監(jiān)護(hù)病房，10位ADC。兩個(gè)定時(shí)器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存
文件頁(yè)數(shù)： 102/106頁(yè)
文件大?。?/td> 1355K
代理商： ST52514K3
14 SERIAL PERIPHERAL INTERFACE (SPI)
14.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master, one or more slaves, or a system, in which
devices may be either masters or slaves.
SPI is normally used for communication between
the ICU and external peripherals or another ICU.
Refer to the Pin Description section in this
datasheet for the device-specific pin-out.
14.2 Main Features
s
Full duplex, three-wire synchronous transfers
s
Master or slave operation
s
Four master mode frequencies
s
Maximum slave mode frequency = CKM/4.
s
Four programmable master bit rates
s
Programmable clock polarity and phase
s
End of transfer interrupt flag
s
Write collision flag protection
s
Master mode fault protection capability.
14.3 General description
SPI is connected to external devices through 4
alternate pins:
– MISO: Master In / Slave Out pin
– MOSI: Master Out / Slave In pin
– SCK: Serial Clock pin
–SS: Slave select pin (if not done through soft-
ware)
Figure 14.1 SPI Master Slave
A basic example of interconnections between a
single master and a single slave is illustrated in
The MOSI pins are connected together as the
MISO pins. In this manner, data is transferred
serially between master and slave (most significant
bit first).
When the master device transmits data to a slave
device via the MOSI pin, the slave device responds
by sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master
device via the SCK pin).
The transmitted byte is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is
complete.
Four possible data/clock timing relationships may
be chosen (see Figure 14.4), but master and slave
must be programmed with the same timing mode.
14.4 Functional Description
Figure 14.2 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (SPI_CR)
– A Status Register (SPI_STATUS_CR)
– A Data Register for transmission (SPI_OUT)
– A Data Register for reception (SPI_OUT)
14.4.1 Master Configuration.
In a master configuration, the serial clock is
generated on the SCK pin.
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
8-BIT SHIFT REGISTER
MISO
MOSI
MISO
SCK
SLAVE
MASTER
SS
+5V
MSBit
LSBit
MSBit
LSBit
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