參數(shù)資料
型號： ST52440G3
英文描述： MAX 7000 CPLD 64 MC 44-TQFP
中文描述： 8位重癥監(jiān)護(hù)病房與定時(shí)器/脈寬調(diào)制。模擬比較器?？煽毓? PWM定時(shí)器。水分散粒劑。提供了8K存儲(chǔ)器
文件頁數(shù)： 46/88頁
文件大?。?/td> 1162K
代理商： ST52440G3
ST52T430/E430
10 PWM/TIMER
ST52x430
offers
three
on-chip
PWM/Timer
peripherals:TIMER0, TIMER1 and TIMER2.
The ST52x430 timers have the same internal
structure. The timer consists of an 8-bit counter
with a 16-bit programmable prescaler, giving a
maximum count of 224 (see Figure 10.1).
Figure 10.1 Timer Peripheral Block Diagram
Next, the generic timer is called Timer x, where x
can be 0, 1 or 2.
Each timer has two different working modes, which
can be selected by setting the correspondent
TxMODE bits of REG_CONF5, REG_CONF8 and
REG_CONF10 registers: Timer Mode and PWM
(Pulse Width Modulation) Mode.
All Timers have Autoreload Functions in PWM
Mode.
Each
timer
output
is
available,
with
its
complementary signal on external pins by setting
PAx
and
PCx
bits
of
REG_CONF12
and
REG_CONF16 (see Table 10.8 and Table 10.9).
Note: In order to enable timer output (TxOUT or
TxOUT) the related pin must be configured in
Output Mode by setting REG_CONF4 and
REG_CONF15 registers (see Table 6.4 and
In particular, TIMER0 can also use external
START/STOP signals (Input capture and Output
compare), external RESET signal and external
CLOCK: PA4/T0STRT, PA0/T0RES and PA5/
T0CLK pins.
Note: In order to use T0RST, T0STR, T0CLK
external signals the related pins must be
configured
in
Input
Mode
by
setting
REG_CONF4 and REG_CONF7 registers (see
For each timer, the content of the 8-bit counter is
incremented on the Rising Edge of the 16-bit
prescaler output (PRESCOUT) and it can be read
at any instant of the counting phase, saved in a
location of RAM memory. The PWM/Timer x
Counter value can be read from the Input Register
PWM_x_COUNT (Input Registers 12, 14 or 16.
The PWM/Timer x Status can be read from the
Input Register PWM_x_STATUS (Input Registers
13, 15 or 17. See Table 2.2 and Table 10.10).
10.1 Timer Mode
Timer Mode is selected by fixing the TxMODE bit
of
REG_CONF5,
REG_CONF8
and
REG_CONF10 equal to 0 (see Table 10.1, Table
Each TIMERx requires three signals: Timer Clock
(TMRCLKx), Timer Reset (TxRES) and Timer Start
(TxSTRT) (see Figure 10.1). Each of these signals
can be generated internally, or, only for Timer 0,
externally by setting T0RST, T0STR, T0CLK bits of
REG_CONF7 register.
TMRCLKx is the Prescaler x output, which
increments the Counter x value on the rising edge.
TMRCLKx is obtained from the internal clock
signal (CLKM) or, only for TIMER0, from the
external signal provided on the PA5/T0CLK pin.
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT14
BIT15
BIT3
BIT0
BIT1
BIT2
BIT6
BIT4
BIT5
BIT7
17- 1MULTIPLEXER
16-BITPRESCALER
8-BITCOUNTER
PRESCx
CLKM
TMRCLK
TxRES
TxSTRT
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
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ST52501LF1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH IR DRIVER. TIMER/PWM. I2C. SPI. SCI. LOW VOLTAGE
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