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| 型號： | ST52440G3 |
| 英文描述： | MAX 7000 CPLD 64 MC 44-TQFP |
| 中文描述： | 8位重癥監(jiān)護病房與定時器/脈寬調(diào)制。模擬比較器。可控硅/ PWM定時器。水分散粒劑。提供了8K存儲器 |
| 文件頁數(shù)： | 29/88頁 |
| 文件大?。?/td> | 1162K |
| 代理商： | ST52440G3 |
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ST52T430/E430
35/88
6 I/O PORTS
6.1 Introduction
ST52x430 devices feature flexible individually
programmable multi-functional input/output lines.
Refer to the following figure for specific pin
allocations.
23 I/O lines, grouped in 3 different ports are
available on the ST52x430:
PORT A = 7 or 8-bit ports (PA0 - PA7 pins)
PORT B = 7 or 8-bit ports (PB0 - PB7 pins)
PORT C = 8-bit port (PC0 - PC7 pins)
PIN 24 in the SO34 or PIN 22 in the PDIP32 can be
configured to belong to port A or to port B.
These I/O lines can be programmed to provide
digital input/output and analog input, or to connect
input/output signals to the on-chip peripherals as
alternate pin functions.
Input buffers are TTL compatible with Schmitt
trigger in port A and C while port B is CMOS
compatible without Schmitt trigger.
The output buffer can supply up to 8 mA.
The port cannot be configured to be used
contemporaneously as input and output.
Figure 6.1 Ports A & C Functional Blocks
Each port is configured by using two configuration
registers. The first is used to determine if a pin is
an input or output, while the second defines the
Alternate functions.
6.2 Input Mode
The input configuration is selected by setting the
corresponding configuration register bit to “1”
(REG_CONF 4, 13 and 15) (see paragraph I/O
Port Configuration Registers). The ports are
configured by using the configuration registers
illustrated in the following table.
.
Digital input data is automatically stored in the
Input Registers, but it cannot be read directly. In
order to read a single bit of the IR its value must be
copied in a RAM location. Digital data is stored in a
RAM location by using the assembler instruction:
LDRI RAM_Reg Input_i
Table 6.1 I/O Port Configuration Registers.
PORT A
PORT B
PORT C
Reg_Conf 4
Reg_Conf 13
Reg_Conf 15
TTL
PORT A PIN
or PORT C PIN
TO INPUT REGISTER
and PERIPHERALS
FROM PERIPHERAL
FROM OUTPUT REGISTER
FROM CONFIGURATION REGISTER
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