參數(shù)資料
型號: ST52440G3
英文描述: MAX 7000 CPLD 64 MC 44-TQFP
中文描述: 8位重癥監(jiān)護病房與定時器/脈寬調制。模擬比較器。可控硅/ PWM定時器。水分散粒劑。提供了8K存儲器
文件頁數(shù): 13/88頁
文件大?。?/td> 1162K
代理商: ST52440G3
ST52T430/E430
2.4 Arithmetic Logic Unit
The 8-bit Arithmetic Logic Unit (ALU) allows the
performance of arithmetic calculations and logic
instructions, which can be divided into 5 groups:
Load, Arithmetic, Jump, Interrupts and Program
Control
instructions
(refer
to
the
ST52x430
Assembler Set for further details).
The
computational
time
required
for
each
instruction consists of one clock pulse for each
Cycle plus 3 clock pulses for the decoding phase.
The
ALU
of
the
ST52x430
can
perform
multiplication
(MULT)
and
division
(DIV).
Multiplication is performed by using 8 bit operands
storing the result in 2 registers (16 bit values), see
WARNING: If the LSB of the multiplication
result is 0, the Zero flag is set although the
result is not 0.
Table 2.4 Output Registers
OR MNEMONIC NAME
PERIPHERAL REGISTER
ADDRESS
PORT_ A
PORT A OR
0
PORT_ B
PORT B OR
1
PORT_C
PORT C OR
2
PWM_0_COUNT
TIMER/PWM 0 COUNTER
3
PWM_0_RELOAD
TIMER/PWM 0 RELOAD REGISTER
4
PWM_1_COUNT
TIMER/PWM 1 COUNTER
5
PWM_1_RELOAD
TIMER/PWM 1 RELOAD REGISTER
6
PWM_ 2_ COUNT
TIMER/PWM 2 COUNTER
7
PWM_2_RELOAD
TIMER/PWM 2 RELOAD REGISTER
8
SCI_TX_DATA
SCI DATA REGISTER
9
Table 2.5 Load instructions
Load Instructions
Mnemonic
Instruction
Bytes
Cycles
Z
S
C
LDCE
LDCE conf, EPROM
3
17
-
LDCR
LDCR conf, RAM
3
14
-
LDFR
LDFR FUZZY_i_RAM RAM
3
14
-
LDPE
LDPE per, EPROM
3
17
-
LDPE
LDPE per, (RAM)
3
17
-
LDPR
LDPR reg, RAM
3
14
-
LDRC
LDRC RAM, const
3
14
-
LDRE
LDRE RAMi, EPROMi
3
16
-
LDRE
LDRE (RAMi), (RAMj)
3
18
-
LDRI
LDRI RAM, inp_reg
3
15
-
LDRR
LDRR RAMi, RAMj
3
16
-
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