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| 型號： | ST52440F2 |
| 英文描述： | MAX 7000 CPLD 64 MC 100-TQFP |
| 中文描述： | 8位重癥監(jiān)護(hù)病房與定時(shí)器/脈寬調(diào)制。模擬比較器?？煽毓? PWM定時(shí)器。水分散粒劑。提供了8K存儲器 |
| 文件頁數(shù)： | 66/88頁 |
| 文件大?。?/td> | 1162K |
| 代理商： | ST52440F2 |
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ST52T430/E430
69/88
Table 12.1 Voltage Characteristics
Symbol
Ratings
Maximum Value
Unit
VDD-VSS
Supply voltage
6.5
V
VDDA-VSSA
Analog reference voltage(VDD≥VDDA)6.5
|V
DDA|and |VSSA|
Variation between different digital power pins
50
mV
|VSSA-VSSX|
Variation between digital and analog ground pins
50
VIN
Input voltage on Vpp
VSS-0.3 to 13
V
Input voltage on any other pin 1) & 2)
VSS-0.3 to VDD+0.3
VDESD
Electro-static discharge voltage
2000
Table 12.2 Current Characteristics
Symbol
Ratings
Maximum Value
Unit
IVDD
Total current in VDD power lines (source)
3)
100
mA
IVSS
Total current in VSS ground lines (sink)
3)
100
IIO
Output current sunk by any standard I/O and control pin
25
Output current source by any I/Os and control pin
-25
IINJ(PIN)
Injected current on VPP pin
±5
Injected current on RESET pin
±5
Injected current on OSCin and OSCout pins
±5
Injected current on any other pin 4)
±5
ΣI
INJ(PIN)
Total Injected current (sum of all I/O and control pins) 4)
±20
Table 12.3 Thermal Characteristics
Symbol
Ratings
Maximum Value
Unit
TSTG
Storage temperature range
-65 to +150
°C
TJ
Maximum junction temperature
150
°C
Notes:
1. Connecting RESET and I/O Pins directly to VDD or VSS could damage the device if the unintentional internal reset is generated
or an unexpected change of I/O configuration occurs (for example, due to the corrupted program counter). In order to guarantee
safe operation, this connection has to be performed via a pull-up or pull-down resistor (typical: 4.7k
for RESET, 10K for I/Os).
Unused I/O pins must be tied in the same manner to VDD or VSS according to their reset configuration.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to I INJ(PIN)
specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSSto I INJ(PIN) specification.
A positive injection is VIN>VDD while a negative injection is induced by VIN<VSS.
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. When several inputs are submitted to a current injection, the maximum
ΣI
INJ(PIN) is the absolute sum of the positive and negative
injected currents (instantaneous values).
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