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| 型號(hào)： | ST52440F2 |
| 英文描述： | MAX 7000 CPLD 64 MC 100-TQFP |
| 中文描述： | 8位重癥監(jiān)護(hù)病房與定時(shí)器/脈寬調(diào)制。模擬比較器。可控硅/ PWM定時(shí)器。水分散粒劑。提供了8K存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 25/88頁(yè) |
| 文件大?。?/td> | 1162K |
| 代理商： | ST52440F2 |
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ST52T430/E430
31/88
Figure 4.6 Example of a sequence of Interrupt requests
REMARK: The Interrupt priority must be set at
the beginning of the main program, because at
the
RESET
REG_CONF1=’00000000’,
this
condition could generate wrong operations.
Further, changing the priority levels must be
avoided in interrupt service routines.
When a source provides an Interrupt request and
the request processing is also enabled, the CU
changes the normal sequential flow of a program
by transferring program control to a selected
service routine.
When an interrupt occurs the CU executes a JUMP
instruction to the address loaded in the related
location of the Interrupt Vector.
When the execution returns to the original program
it immediately begins following the instruction that
was interrupted.
4.6 Interrupts and Low power mode
All interrupts allow the processor to leave the WAIT
low power mode. Only the external Interrupt allows
the processor to leave the HALT low power mode.
4.7 Interrupt RESET
An eventually pending interrupt can be reset with
the instruction RINT j, which resets the interrupt
j-th where j identifies the peripherals as described
in the following table (see Table 4.4).
The assembler instruction:
RINT 2
Resets the PWM/Timer 1 interrupt.
Note: The RINT command must be preceded
from a UDGI (or MDGI) command and followed
by a UEGI (or MEGI) command.
WARNING: If an interrupt is reset, with the RINT
instruction within its own interrupt routine, the
priority level of the interrupt becomes the
lowest and the routine can be immediately
interrupted
by
a
lower
priority
interrupt
request.
Table 4.4 RINT Instruction code
Peripheral Name
Value
A/D Converter
0
PWM/TIMER 0
1
PWM/TIMER 1
2
PWM/TIMER 2
3
SCI
4
External Interrupt
5
Table 4.4 RINT Instruction code
Peripheral Name
Value
MAIN PROGRAM
5
4
3
2
1
0
INT2
INT0
INT2
INT1
INT2
INT3
INT4
MAIN PROGRAM
PRIORITY
LEVEL
INT2
INT0
INT4
INT1
INT3
6
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| ST52501LF1 | MAX 7000 CPLD 128 MC 84-PLCC |
| ST52501LF2 | MAX 7000 CPLD 128 MC 100-TQFP |
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| ST52440G3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH TIMER/PWM. ANALOG COMPARATOR. TRIAC/PWM TIMER. WDG. UP TO 8K EPROM |
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