參數資料
型號： ST52440F2
英文描述： MAX 7000 CPLD 64 MC 100-TQFP
中文描述： 8位重癥監(jiān)護病房與定時器/脈寬調制。模擬比較器。可控硅/ PWM定時器。水分散粒劑。提供了8K存儲器
文件頁數： 63/88頁
文件大?。?/td> 1162K
代理商： ST52440F2
ST52T430/E430
A frame error can occur if the parity check hasn’t
been successfully achieved or if the STOP bit
hasn’t been detected.
If
the
Recovery
Buffer
Block
receives
10
consecutive bits at logic level 0, a break error
occurs and an interrupt routine request starts.
SCDR_RX Block
It is a finite state machine synchronized with the
clock master signal, CKM.
The SCDR_RX block waits for the signal of
complete reception from the Recovery Buffer, in
order to load the word received. Moreover, the
SCDR_RX block loads the values of FRERR and
NSERR flag bits (Input Register 19), and sets the
RXF flag to 1.
Data is transferred to RAM and the RXF flag is
reset to 0 by using the LDRI instruction in order to
indicate that the SCDR_RX block is empty.
If new data arrives before the previous one has
been transferred to Register File, an overrun error
occurs and OVERR flag of Input Register 19 is set
to 1.
11.2 SCI Transmitter Block
The SCI Transmitter Block consists of the following
blocks:
SCDR_TX
and
SHIFT
REGISTER,
synchronized, respectively, with the clock master
signal (CKM) and the CLOCK_TX.
The whole block receives the settings for the
following transmission modes (see Table 11.1)
through Configuration Register 20 (M bits):
s
8-bit word and a single stop signal
s
8-bit word plus a parity bit and a single stop
signal
s
8-bit word plus a double stop signal
s
9-bit word
In case of 9 bit frame transmission, the most
significative
bit
arrives
through
T8
of
the
Configuration Register 20.
Instead, in an 8-bit transmission T8 is used to
configure SCI according to information contained
in M (see Table 11.1). In particular, it is used to
choose the polarity control (even or odds) in order
to implement the parity check.
After a RESET signal RST, the SCDR_TX block is
in IDLE state until it receives the enabling signal
TE=1, of Configuration Register 20.
Data is loaded on the peripheral register (OR 9) by
using the instruction LPPR or LDPE. If TE=1 the
data to be transmitted is transferred from DR_TX
block and flag of Input Register 19. TXEM is reset
to 0 in order to indicate that the SCDR_TX block is
full.
Table 11.2 Configuration Register 19 Setting
Bit
Name
Value
Description
0
-
Not used
1
ECKF
00
5 MHz
01
10 MHz
2
10
20 MHz
11
5 MHz
3
TXC
0
SCI End
Transmission
Interrupt Disabled
1
SCI End
Transmission
Interrupt Enabled
4
TDRE
0
SCI Transmission
Data Register Empty
Interrupt Disabled
1
SCI Transmission
Data Register Empty
Interrupt Enabled
5
BRK
0
SCI Break Error
Interrupt Disabled
1
SCI Break Error
Interrupt Enabled
6
OVR
0
SCI Overrun Error
Interrupt Disabled
1
SCI Overrun Error
Interrupt Enabled
7
RDRF
0
SCI Received Data
Register Full Interrupt
Disabled
1
SCI Received Data
Register Full Interrupt
Enabled
相關PDF資料
PDF描述
ST52440F3 MAX 7000 CPLD 64 MC 44-TQFP
ST52440G2 MAX 7000 CPLD 64 MC 44-TQFP
ST52440G3 MAX 7000 CPLD 64 MC 44-TQFP
ST52501LF1 MAX 7000 CPLD 128 MC 84-PLCC
ST52501LF2 MAX 7000 CPLD 128 MC 100-TQFP
相關代理商/技術參數
參數描述
ST52440F3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH TIMER/PWM. ANALOG COMPARATOR. TRIAC/PWM TIMER. WDG. UP TO 8K EPROM
ST52440G2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH TIMER/PWM. ANALOG COMPARATOR. TRIAC/PWM TIMER. WDG. UP TO 8K EPROM
ST52440G3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH TIMER/PWM. ANALOG COMPARATOR. TRIAC/PWM TIMER. WDG. UP TO 8K EPROM
ST5-24B19 功能描述:電源變壓器 SPLIT BOBBIN HORZ MOUNT XFMR RoHS:否 制造商:Triad Magnetics 功率額定值:12 VA 初級電壓額定值:115 V / 230 V 次級電壓額定值:12 V / 24 V 安裝風格:SMD/SMT 一次繞組:Dual Primary Winding 二次繞組:Dual Secondary Winding 長度:2.5 in 寬度:2 in 高度:1.062 in
ST525 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | BJT | NPN | 200V V(BR)CEO | 5A I(C) | TO-3
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯系方式

*
*
*