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參數(shù)資料
| 型號(hào)： | ST16C580 |
| 廠商： | Exar Corporation |
| 英文描述： | UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER |
| 中文描述： | UART的16字節(jié)FIFO的和紅外線（IrDA）編碼/解碼器 |
| 文件頁(yè)數(shù)： | 16/41頁(yè) |
| 文件大?。?/td> | 244K |
| 代理商： | ST16C580 |
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ST16C580
16
Rev. 1.20
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the fifteen 580 internal registers. The assigned
bit functions are more fully defined in the following paragraphs.
Table 5, ST16C580 INTERNAL REGISTERS
A2 A1 A0
Register
[Default]
Note *5
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
General Register Set
0
0
0
RHR [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
0
0
THR [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
0
1
IER [00]
CTS
interrupt
RTS
interrupt
Xoff
Sleep
mode
modem
status
interrupt
receive
line
status
interrupt
transmit
holding
register
receive
holding
register
interrupt
0
1
0
FCR [00]
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
TX
TX
DMA
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFO
enable
trigger
(MSB)
trigger
(LSB)
0
1
0
ISR [01]
FIFO’s
enabled
FIFO’s
enabled
INT
priority
bit-4
INT
priority
bit-3
INT
priority
bit-2
INT
priority
bit-1
INT
priority
bit-0
INT
status
0
1
1
LCR [00]
divisor
latch
enable
set
break
set
parity
even
parity
parity
enable
stop
bits
word
length
bit-1
word
length
bit-0
1
0
0
MCR [00]
Clock
select
IR
0
loop
back
-OP2
-OP1
-RTS
-DTR
enable
1
0
1
LSR [60]
FIFO
data
error
trans.
empty
trans.
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
1
0
MSR [X0]
CD
RI
DSR
CTS
delta
-CD
delta
-RI
delta
-DSR
delta
-CTS
1
1
1
SPR [FF]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
Special Register Set: Note *3
0
0
0
DLL [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
0
1
DLM [XX]
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
bit-9
bit-8
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