參數(shù)資料
型號(hào): ST16C554DIQ64
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: QUAD UART WITH 16-BYTE FIFOS
中文描述: 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64
文件頁數(shù): 6/40頁
文件大?。?/td> 518K
代理商: ST16C554DIQ64
ST16C554/554D/68C554
6
Rev. 3.10
SYMBOL DESCRIPTION
Symbol
Pin
Signal
type
Pin Description
68
64
-CS A-B
-CS C-D
16,20
50,54
7,11
38,42
I
Chip Select A, B, C, D (active low) - This function is
associated with the 16 mode only, and for individual chan-
nels, A through D. When in 16 Mode, these pins enable
data transfers between the user CPU and the ST16C554D
for the channel(s) addressed. Individual UART sections (A,
B, C, D) are addressed by providing a logic 0 on the
respective -CS A-D pin. When the 68 mode is selected, the
functions of these pins are reassigned. 68 mode functions
are described under the their respective name/pin head-
ings.
D0-D2
D3-D7
66-68
1-5
53-55
56-60
I/O
Data Bus (Bi-directional) - These pins are the eight bit, three
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
GND
GND
6,23
40,57
14,28
45,61
Pwr
Signal and power ground.
INT A-B
INT C-D
15,21
49,55
6,12
37,43
O
Interrupt A, B, C, D (active high) - This function is associated
with the 16 mode only. These pins provide individual
channel interrupts, INT A-D. INT A-D are enabled when
MCR bit-3 is set to a logic 1, interrupts are enabled in the
interrupt enable register (IER), and when an interrupt con-
dition exists. Interrupt conditions include: receiver errors,
available receiver buffer data, transmit buffer empty, or
when a modem status flag is detected. When the 68 mode
is selected, the functions of these pins are reassigned. 68
mode functions are described under the their respective
name/pin headings.
INTSEL
65
-
I
Interrupt Select. (active high, with internal pull-down) - This
function is associated with the 16 mode only. When the 16
mode is selected, this pin can be used in conjunction with
MCR bit-3 to enable or disable the three state interrupts, INT
A-D or override MCR bit-3 and force continuous interrupts.
Interrupt outputs are enabled continuously by making this
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