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參數(shù)資料
| 型號(hào)： | ST16C554DIQ64 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | QUAD UART WITH 16-BYTE FIFOS |
| 中文描述： | 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64 |
| 文件頁數(shù)： | 21/40頁 |
| 文件大小： | 518K |
| 代理商： | ST16C554DIQ64 |
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ST16C554/554D/68C554
21
Rev. 3.10
ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
ISR BIT 1-3: (logic 0 or cleared is the default condition)
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, and 3 (See Interrupt
Source Table).
ISR BIT 4-5:
Not used - Initialized to a logic 0.
ISR BIT 6-7: (logic 0 or cleared is the default condition)
These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFOs
are enabled.
Line Control Register (LCR)
The Line Control Register is used to specify the
asynchronous data communication format. The word
length, the number of stop bits, and the parity are
selected by writing the appropriate bits in this register.
LCR BIT 0-1: (logic 0 or cleared is the default condi-
tion)
These two bits specify the word length to be transmit-
ted or received.
BIT-1
BIT-0
Word length
0
0
1
1
0
1
0
1
5
6
7
8
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in
conjunction with the programmed word length.
BIT-2
Word length
Stop bit
length
(Bit time(s))
0
1
1
5,6,7,8
5
6,7,8
1
1-1/2
2
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity. (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, receiver checks the data and parity for transmis-
sion errors.
LCR BIT-4:
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1s in the transmitted data. The
receiver must be programmed to check the same
format. (normal default condition)
Logic 1 = EVEN Parity
is generated by forcing an even
the number of logic 1s in the transmitted. The receiver
must be programmed to check the same format.
LCR BIT-5:
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
LCR BIT-5 = logic 0, parity is not forced. (normal
default condition)
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit
is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit
is forced to a logical 0 for the transmit and receive
data.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST16C554CQ64 | Linear Voltage Regulator IC; Output Current Max:350mA; Supply Voltage Max:6V; Package/Case:8-TSSOP; Current Rating:350mA; Leaded Process Compatible:No; Output Voltage Max:2.8V; Peak Reflow Compatible (260 C):No |
| ST16C554DCQ64 | QUAD UART WITH 16-BYTE FIFOS |
| ST16C554 | Quad UART with 16-Byte FIFO(四通用異步接收器/發(fā)送器（帶16字節(jié)的先進(jìn)先出）) |
| ST16C554D | Quad UART with 16-Byte FIFO(四通用異步接收器/發(fā)送器（帶16字節(jié)的先進(jìn)先出）) |
| ST16C580 | UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C554DIQ64-F | 功能描述:UART 接口集成電路 2.97V-5.5V 16B FIFO temp -45 to 85C;UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C554DIQ64TR-F | 功能描述:UART 接口集成電路 QUAD UART W/16 BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C554ECQ64 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| ST16C554EDCJ68 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| ST16C554EDCQ64 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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