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參數(shù)資料
| 型號(hào)： | ST16C554DIQ64 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | QUAD UART WITH 16-BYTE FIFOS |
| 中文描述： | 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64 |
| 文件頁數(shù)： | 23/40頁 |
| 文件大?。?/td> | 518K |
| 代理商： | ST16C554DIQ64 |
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ST16C554/554D/68C554
23
Rev. 3.10
have a valid stop bit(s). In the FIFO mode this error is
associated with the character at the top of the FIFO.
LSR BIT-4:
Logic 0 = No break condition. (normal default condi-
tion)
Logic 1 = The receiver received a break signal (RX
was a logic 0 for one character frame time). In the
FIFO mode, only one break character is loaded into
the FIFO.
LSR BIT-5:
This bit is the Transmit Holding Register Empty indi-
cator. This bit indicates that the UART is ready to
accept a new character for transmission. In addition,
this bit causes the UART to issue an interrupt to CPU
when the THR interrupt enable is set. The THR bit is
set to a logic 1 when a character is transferred from the
transmit holding register into the transmitter shift
register. The bit is reset to logic 0 concurrently with the
loading of the transmitter holding register by the CPU.
In the FIFO mode this bit is set when the transmit FIFO
is empty; it is cleared when at least 1 byte is written to
the transmit FIFO.
LSR BIT-6:
This bit is the Transmit Empty indicator. This bit is set
to a logic 1 whenever the transmit holding register and
the transmit shift register are both empty. It is reset to
logic 0 whenever either the THR or TSR contains a
data character. In the FIFO mode this bit is set to one
whenever the transmit FIFO and transmit shift register
are both empty.
LSR BIT-7:
Logic 0 = No Error. (normal default condition)
Logic 1 = At least one parity error, framing error or
break indication is in the current FIFO data. This bit is
cleared when LSR register is read.
Modem Status Register (MSR)
This register provides the current state of the control
interface signals from the modem, or other peripheral
device that the 554D is connected to. Four bits of this
register are used to indicate the changed information.
These bits are set to a logic 1 whenever a control input
from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.
MSR BIT-0:
Logic 0 = No -CTS Change (normal default condition)
Logic 1 = The -CTS input to the 554D has changed
state since the last time it was read. A modem Status
Interrupt will be generated.
MSR BIT-1:
Logic 0 = No -DSR Change. (normal default condition)
Logic 1 = The -DSR input to the 554D has changed
state since the last time it was read. A modem Status
Interrupt will be generated.
MSR BIT-2:
Logic 0 = No -RI Change. (normal default condition)
Logic 1 = The -RI input to the 554D has changed from
a logic 0 to a logic 1. A modem Status Interrupt will be
generated.
MSR BIT-3:
Logic 0 = No -CD Change. (normal default condition)
Logic 1 = Indicates that the -CD input to the has
changed state since the last time it was read. A
modem Status Interrupt will be generated.
MSR BIT-4:
-CTS (active high, logical 1). Normally MSR bit-4 bit
is the compliment of the -CTS input. However in the
loopback mode, this bit is equivalent to the RTS bit in
the MCR register.
MSR BIT-5:
DSR (active high, logical 1). Normally this bit is the
compliment of the -DSR input. In the loopback mode,
this bit is equivalent to the DTR bit in the MCR register.
MSR BIT-6:
RI (active high, logical 1). Normally this bit is the
compliment of the -RI input. In the loopback mode this
bit is equivalent to the OP1 bit in the MCR register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST16C554CQ64 | Linear Voltage Regulator IC; Output Current Max:350mA; Supply Voltage Max:6V; Package/Case:8-TSSOP; Current Rating:350mA; Leaded Process Compatible:No; Output Voltage Max:2.8V; Peak Reflow Compatible (260 C):No |
| ST16C554DCQ64 | QUAD UART WITH 16-BYTE FIFOS |
| ST16C554 | Quad UART with 16-Byte FIFO(四通用異步接收器/發(fā)送器（帶16字節(jié)的先進(jìn)先出）) |
| ST16C554D | Quad UART with 16-Byte FIFO(四通用異步接收器/發(fā)送器（帶16字節(jié)的先進(jìn)先出）) |
| ST16C580 | UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ST16C554DIQ64-F | 功能描述:UART 接口集成電路 2.97V-5.5V 16B FIFO temp -45 to 85C;UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C554DIQ64TR-F | 功能描述:UART 接口集成電路 QUAD UART W/16 BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C554ECQ64 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| ST16C554EDCJ68 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| ST16C554EDCQ64 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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